Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 21-9
VMX NON-ROOT OPERATION
These principles imply among other things, that an APIC-access VM exit may occur
during the execution of a repeated string instruction (including INS and OUTS).
Suppose, for example, that the first n iterations (n may be 0) of such an instruction
do not access the APIC-access page and that the next iteration does access that
page. As a result, the first n iterations may complete and be followed by an APIC-
access VM exit. The instruction pointer saved in the VMCS references the repeated
string instruction and the values of the general-purpose registers reflect the comple-
tion of n iterations.
21.2.1.3 Instructions That May Cause Page Faults or EPT Violations
Without Accessing Memory
APIC-access VM exits may occur as a result of executing an instruction that can
cause a page fault or an EPT violation even if that instruction would not access the
APIC-access page. The following are some examples:
• The CLFLUSH instruction is considered to read from the linear address in its
source operand. If that address translates to one on the APIC-access page, the
instruction causes an APIC-access VM exit.
• The ENTER instruction causes a page fault if the byte referenced by the final
value of the stack pointer is not writable (even though ENTER does not write to
that byte if its size operand is non-zero). If that byte is writable but is on the
APIC-access page, ENTER causes an APIC-access VM exit.
1
• An execution of the MASKMOVQ or MASKMOVDQU instructions with a zero mask
may or may not cause a page fault or an EPT violation if the destination page is
unwritable (the behavior is implementation-specific). An execution with a zero
mask causes an APIC-access VM exit only on processors for which it could cause
a page fault or an EPT violation.
• The MONITOR instruction is considered to read from the effective address in RAX.
If the linear address corresponding to that address translates to one on the APIC-
access page, the instruction causes an APIC-access VM exit.
2
• An execution of the PREFETCH instruction that would result in an access to the
APIC-access page does not cause an APIC-access VM exit.
1. The ENTER instruction may also cause page faults due to the memory accesses that it actually
does perform. With regard to APIC-access VM exits, these are treated just as accesses by any
other instruction.
2. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most
processors that support VMX operation also support Intel 64 architecture. For IA-32 processors,
this notation refers to the 32-bit forms of those registers (EAX, EIP, ESP, EFLAGS, etc.). In a few
places, notation such as EAX is used to refer specifically to lower 32 bits of the indicated regis-
ter.