Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

21-10 Vol. 3
VMX NON-ROOT OPERATION
21.2.2 Guest-Physical Accesses to the APIC-Access Page
An access to the APIC-access page is called a guest-physical access if (1) guest-
physical addresses are being translated using EPT (see Chapter 24); (2) the access’s
physical address is the result of an EPT translation; and (3) either (a) the access was
not generated by a linear address; or (b) the access’s guest-physical address is not
the translation of the access’s linear address. Guest-physical accesses include the
following when guest-physical addresses are being translated using EPT:
• Reads from the guest paging structures when translating a linear address (such
an access uses a guest-physical address that is not the translation of that linear
address).
• Loads of the page-directory-pointer-table entries by MOV to CR when the logical
processor is using (or that causes the logical processor to use) PAE paging.
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• Updates to the accessed and dirty bits in the guest paging structures when using
a linear address (such an access uses a guest-physical address that is not the
translation of that linear address).
Section 21.2.2.1 specifies when guest-physical accesses to the APIC-access page
might not cause APIC-access VM exits. In general, the treatment of APIC-access
VM exits caused by guest-physical accesses is similar to that of EPT violations. Based
upon this treatment, Section 21.2.2.2 specifies the priority of such VM exits with
respect to other events.
21.2.2.1 Guest-Physical Accesses That Might Not Cause APIC-Access
VM Exits
Whether a guest-physical access to the APIC-access page causes an APIC-access
VM exit depends on the nature of the EPT translation used by the guest-physical
address and on how software is managing information cached from the EPT paging
structures. The following items detail cases in which a guest-physical access to the
APIC-access page might not an APIC-access VM exit:
• If the access uses a guest-physical address whose translation to the APIC-access
page uses an EPT PDE that maps a 2-MByte page (because bit 7 of the EPT PDE
is 1).
• Software has not properly invalidated information cached from the EPT paging
structures:
— At time t
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, EPT was in use, the EPTP value was X, and some guest-physical
address Y translated to an address that was not on the APIC-access page at
that time. (This might be because the “virtualize APIC accesses” VM-
execution control was 0.)
— At later time t
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, the EPTP value is X and a memory access uses guest-physical
address Y, which now translates to an address on the APIC-access page. (This
1. A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1 and IA32_EFER.LMA = 0. See
Section 3.8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.