Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

21-12 Vol. 3
VMX NON-ROOT OPERATION
— Updates to the accessed and dirty bits in the paging structures.
• If the “enable EPT” VM-execution control is 1, accesses to the EPT paging
structures.
• Any of the following accesses made by the processor to support VMX non-root
operation:
— Accesses to the VMCS region.
— Accesses to data structures referenced (directly or indirectly) by physical
addresses in VM-execution control fields in the VMCS. These include the I/O
bitmaps, the MSR bitmaps, and the virtual-APIC page.
• Accesses that effect transitions into and out of SMM.
1
These include the
following:
— Accesses to SMRAM during SMI delivery and during execution of RSM.
— Accesses during SMM VM exits (including accesses to MSEG) and during
VM entries that return from SMM.
A physical access to the APIC-access page may or may not cause an APIC-access
VM exit. (A physical write to the APIC-access page may write to memory as specified
in Section 21.5.2 before causing the APIC-access VM exit.) The priority of an APIC-
access VM exit caused by physical access is not defined relative to other events that
the access may cause. Section 21.5.2 describes the treatment of physical accesses to
the APIC-access page that do not cause APIC-access VM exits.
It is recommended that software not set the APIC-access address to any of those
used by physical memory accesses (identified above). For example, it should not set
the APIC-access address to the physical address of any of the active paging struc-
tures if the “enable EPT” VM-execution control is 0.
21.2.4 VTPR Accesses
A memory access is a VTPR access if all of the following hold: (1) the “use TPR
shadow” VM-execution control is 1; (2) the access is not for an instruction fetch;
(3) the access is at most 32 bits in width; and (4) the access is to offset 80H on the
APIC-access page.
A memory access is not a VTPR access (even if it accesses only bytes in the range
80H–83H on the APIC-access page) if any of the following hold: (1) the “use TPR
shadow” VM-execution control is 0; (2) the access is for an instruction fetch; (3) the
access is more than 32 bits in width; or (4) the access is to some offset is on the
APIC-access page other than 80H. For example, a 16-bit access to offset 81H on the
2. A logical processor uses PAE paging if CR0.PG = 1, CR4.PAE = 1 and IA32_EFER.LMA = 0. See
Section 3.8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
1. Technically, these accesses do not occur in VMX non-root operation. They are included here for
clarity.