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Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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Table Of Contents
Vol. 3 18-19
DEBUGGING AND PERFORMANCE MONITORING
Software must re-enable counts by writing 1s to the corresponding enable bits in
MSR_PERF_GLOBAL_CTRL before leaving a PMI service routine to continue
counter operation.
Freezing LBRs and PMCs on PMIs occur when:
• A performance counter had an overflow and was programmed to signal a PMI in
case of an overflow.
— For the general-purpose counters; this is done by setting bit 20 of the
IA32_PERFEVTSELx register.
— For the fixed-function counters; this is done by setting the 3rd bit in the
corresponding 4-bit control field of the MSR_PERF_FIXED_CTR_CTRL register
(see Figure 18-21) or IA32_FIXED_CTR_CTRL MSR (see Figure 18-14).
• The PEBS buffer is almost full and reaches the interrupt threshold.
• The BTS buffer is almost full and reaches the interrupt threshold.
18.5.3.2 Debug Store (DS) Mechanism
The debug store mechanism provides the DS save area for software to collect branch
records or precise-event-based-sampling (PEBS) records. Fields in the buffer
management area of a DS save area are described in Section 18.18.5.
The format of a branch trace record and a PEBS record are the same as the 64-bit
record formats shown in Figures 18-42 and Figures 18-43, with the exception that
the branch predicted bit is not supported by Intel Core microarchitecture. The 64-bit
record formats for BTS and PEBS apply to DS save area for all operating modes.
The procedures used to program IA32_DEBUG_CTRL MSR to set up a BTS buffer or a
CPL-qualified BTS are described in Section 18.7.8.3 and Section 18.7.8.4.
Required elements for writing a DS interrupt service routine are largely the same as
those described in Section 18.7.8.5. However, instead of re-enabling counting using
CCCRs like on processors based on Intel NetBurst
®
microarchitecture, a DS interrupt
service routine on processors based on Intel Core or Intel Atom microarchitecture
should:
• Re-enable the enable bits in MSR_PERF_GLOBAL_CTRL MSR if it is servicing an
overflow PMI due to PEBS.
• Clear overflow indications by writing to MSR_PERF_GLOBAL_OVF_CTRL when a
counting configuration is changed. This includes bit 62 (ClrOvfBuffer) and the
overflow indication of counters used in either PEBS or general-purpose counting
(specifically: bits 0 or 1; see Figures 18-24).