Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

21-20 Vol. 3
VMX NON-ROOT OPERATION
processor is not in VMX non-root operation). Otherwise, instruction behavior
is determined by the setting of the “virtualize x2APIC mode” VM-execution
control and the value of the TPR-threshold VM-execution control field:
• If the control is 0, the instruction operates normally. If the local APIC is in
x2APIC mode, the value of EAX[7:0] is written to the APIC’s task-priority
register. If the local APIC is not in x2APIC mode, a general-protection
fault occurs.
• If the control is 1, the instruction stores the value of EAX:EDX to
bytes 87H:80H of the virtual-APIC page. This store occurs even if the
local APIC is not in x2APIC mode (no general-protection fault occurs
because the local APIC is not x2APIC mode). The store may cause a
VM exit to occur after the instruction completes (see Section 21.1.3).
21.5 APIC ACCESSES THAT DO NOT CAUSE VM EXITS
As noted in Section 21.2, if the “virtualize APIC accesses” VM-execution control is 1,
most memory accesses to the APIC-access page (see Section 20.6.8) cause APIC-
access VM exits.
1
Section 21.2 identifies potential exceptions. These are covered in
Section 21.5.1 through Section 21.5.3.
In some cases, an attempt to access memory on the APIC-access page is converted
to an access to the virtual-APIC page (see Section 20.6.8). In these cases, the access
uses the memory type reported in bit 53:50 of the IA32_VMX_BASIC MSR (see
Appendix G.1).
21.5.1 Linear Accesses to the APIC-Access Page Using Large-Page
Translations
As noted in Section 21.2.1, a linear access to the APIC-access page using translation
with a large page (2-MByte or 4-MByte) may or may not cause an APIC-access
VM exit. If it does not and the access is not a VTPR access (see Section 21.2.4), the
access operates on memory on the APIC-access page. Section 21.5.3 describes the
treatment if there is no APIC-access VM exit and the access is a VTPR access.
21.5.2 Physical Accesses to the APIC-Access Page
A physical access to the APIC-access page may or may not cause an APIC-access
VM exit. If it does not and the access is not a VTPR access (see Section 21.2.4), the
access operates on memory on the APIC-access page (this may happen if the access
1. Note that “virtualize APIC accesses” is a secondary processor-based VM-execution control. If
bit 31 of the primary processor-based VM-execution controls is 0, VMX non-root operation func-
tions as if the “virtualize APIC accesses” VM-execution control were 0. See Section 20.6.2.