Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

21-22 Vol. 3
VMX NON-ROOT OPERATION
— A VTPR access using the CLFLUSH instruction flushes data for offset 80H on
the virtual-APIC page.
— A VTPR access using the LMSW instruction may cause a VM exit due to the
CR0 guest/host mask and the CR0 read shadow.
— A VTPR access using the MONITOR instruction causes the logical processor to
monitor offset 80H on the virtual-APIC page.
— A VTPR access using the PREFETCH instruction may prefetch data; if so, it is
from offset 80H on the virtual-APIC page.
• VTPR write accesses. Such an access completes normally (writing data to the
field at offset 80H on the virtual-APIC page) and causes a TPR-shadow update
(see Section 21.5.3.3).
The following items detail certain instructions that are considered to perform
write accesses and how they behavior when accessing the VTPR:
— The ENTER instruction is considered to write to VTPR if the byte referenced by
the final value of the stack pointer is at offset 80H on the APIC-access page
(even though ENTER does not write to that byte if its size operand is non-
zero). The instruction is followed by a TPR-shadow update.
— A VTPR access using the SMSW instruction stores data determined by the
current CR0 contents, the CR0 guest/host mask, and the CR0 read shadow.
The instruction is followed by a TPR-shadow update.
21.5.3.2 Operations with Multiple Accesses
Some operations may access multiple addresses. These operations include the
execution of some instructions and the delivery of events through the IDT (including
those injected with VM entry). In some cases, the Intel
®
64 architecture specifies the
ordering of these memory accesses. The following items describe the treatment of
VTPR accesses that are part of such multi-access operations:
• Read-modify-write instructions may first perform a VTPR read access and then a
VTPR write access. Both accesses complete normally (as described in Section
21.5.3.1). The instruction is followed by a TPR-shadow update (see Section
21.5.3.3).
• Some operations may perform a VTPR write access and subsequently cause a
fault. This situation is treated as follows:
— If the fault leads to a VM exit, no TPR-shadow update occurs.
— If the fault does not lead to a VM exit, a TPR-shadow update occurs after fault
delivery completes and before execution of the fault handler.
• If an operation includes a VTPR access and an access to some other field on the
APIC-access page, the latter access causes an APIC-access VM exit as described
in Section 21.2.
If the operation performs a VTPR write access before the APIC-access VM exit,
there is no TPR-shadow update.