Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 21-23
VMX NON-ROOT OPERATION
• Suppose that the first iteration of a repeated string instruction (including OUTS)
that accesses the APIC-access page performs a VTPR read access and that the
next iteration would read from the APIC-access page using an offset other than
80H. The following items describe the behavior of the logical processor:
— The iteration that performs the VTPR read access completes successfully,
reading data from offset 80H on the virtual-APIC page.
— The iteration that would read from the other offset causes an APIC-access
VM exit. The instruction pointer saved in the VMCS references the repeated
string instruction and the values of the general-purpose registers are such
that iteration would be repeated if the instruction were restarted.
• Suppose that the first iteration of a repeated string instruction (including INS)
that accesses the APIC-access page performs a VTPR write access and that the
next iteration would write to the APIC-access page using an offset other than
80H. The following items describe the behavior of the logical processor:
— The iteration that performs the VTPR write access writes data to offset 80H on
the virtual-APIC page. The write is followed by a TPR-shadow update, which
may cause a VM exit (see Section 21.5.3.3).
— If the TPR-shadow update does cause a VM exit, the instruction pointer saved
in the VMCS references the repeated string instruction and the values of the
general-purpose registers are such that the next iteration would be
performed if the instruction were restarted.
— If the TPR-shadow update does not cause a VM exit, the iteration that would
write to the other offset causes an APIC-access VM exit. The instruction
pointer saved in the VMCS references the repeated string instruction and the
values of the general-purpose registers are such that that iteration would be
repeated if the instruction were restarted.
• Suppose that the last iteration of a repeated string instruction (including INS)
performs a VTPR write access. The iteration writes data to offset 80H on the
virtual-APIC page. The write is followed by a TPR-shadow update, which may
cause a VM exit (see Section 21.5.3.3). If it does, the instruction pointer saved in
the VMCS references the instruction after the string instruction and the values of
the general-purpose registers reflect completion of the string instruction.
21.5.3.3 TPR-Shadow Updates
If the “use TPR shadow” and “virtualize APIC accesses” VM-execution controls are
both 1, a logical processor performs certain actions after any operation (or iteration
of a repeated string instruction) with a VTPR write access. These actions are called a
TPR-shadow update. (As noted in Section 21.5.3.2, a TPR-shadow update does not
occur following an access that causes a VM exit.)
A TPR-shadow update includes the following actions:
1. Bits 31:8 at offset 80H on the virtual-APIC page are cleared.