Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 22-7
VM ENTRIES
• Fields relevant to VM-entry event injection must be set properly. These fields are
the VM-entry interruption-information field (see Table 20-12 in Section 20.8.3),
the VM-entry exception error code, and the VM-entry instruction length. If the
valid bit (bit 31) in the VM-entry interruption-information field is 1, the following
must hold:
— The field’s interruption type (bits 10:8) is not set to a reserved value. Value 1
is reserved on all logical processors; value 7 (other event) is reserved on
logical processors that do not support the 1-setting of the “monitor trap flag”
VM-execution control.
— The field’s vector (bits 7:0) is consistent with the interruption type:
• If the interruption type is non-maskable interrupt (NMI), the vector is 2.
• If the interruption type is hardware exception, the vector is at most 31.
• If the interruption type is other event, the vector is 0 (pending MTF
VM exit).
— The field’s deliver-error-code bit (bit 11) is 1 if and only if the interruption
type is hardware exception and the vector indicates an exception that would
normally deliver an error code (8 = #DF; 10 = TS; 11 = #NP; 12 = #SS;
13 = #GP; 14 = #PF; or 17 = #AC).
— Reserved bits in the field (30:12) are 0.
— If the deliver-error-code bit (bit 11) is 1, bits 31:15 of the VM-entry
exception error-code field are 0.
— If the interruption type is software interrupt, software exception, or
privileged software exception, the VM-entry instruction-length field is in the
range 1–15.
• The following checks are performed for the VM-entry MSR-load address if the
VM-entry MSR-load count field is non-zero:
— The lower 4 bits of the VM-entry MSR-load address must be 0. On processors
that support Intel 64 architecture, the address should not set any bits beyond
the processor’s physical-address width.
1
On processors that do not support
Intel 64 architecture, the address should not set any bits in the range 63:32.
— On processors that support Intel 64 architecture, the address of the last byte
in the VM-entry MSR-load area should not set any bits beyond the processor’s
physical-address width. On processors that do not support Intel 64 archi-
tecture, the address of the last byte in the VM-entry MSR-load area should
not set any bits in the range 63:32. The address of this last byte is VM-entry
MSR-load address + (MSR count * 16) – 1. (The arithmetic used for the
computation uses more bits than the processor’s physical-address width.)
1. Software can determine a processor’s physical-address width by executing CPUID with
80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.