Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

22-10 Vol. 3
VM ENTRIES
22.3.1 Checks on the Guest State Area
This section describes checks performed on fields in the guest-state area. These
checks may be performed in any order. The following subsections reference fields
that correspond to processor state. Unless otherwise stated, these references are to
fields in the guest-state area.
22.3.1.1 Checks on Guest Control Registers, Debug Registers, and MSRs
The following checks are performed on fields in the guest-state area corresponding to
control registers, debug registers, and MSRs:
• The CR0 field must not set any bit to a value not supported in VMX operation
(see Section 19.8).
1
• The CR4 field must not set any bit to a value not supported in VMX operation
(see Section 19.8).
• If the “load debug controls” VM-entry control is 1, bits reserved in the
IA32_DEBUGCTL MSR must be 0 in the field for that register. Note that the first
processors to support the virtual-machine extensions supported only the 1-
setting of this control and thus performed this check unconditionally.
• The following checks are performed on processors that support Intel 64 archi-
tecture:
— If the “IA-32e mode guest” VM-entry control is 1, bit 5 in the CR4 field (corre-
sponding to CR4.PAE) must be 1.
— The CR3 field must be such that bits 63:52 and bits in the range 51:32
beyond the processor’s physical-address width are 0.
2
— If the “load debug controls” VM-entry control is 1, bits 63:32 in the DR7 field
must be 0. Note that the first processors to support the virtual-machine
extensions supported only the 1-setting of this control and thus performed
this check unconditionally (if they supported Intel 64 architecture).
— The IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field must each
contain a canonical address.
• If the “load IA32_PERF_GLOBAL_CTRL” VM-entry control is 1, bits reserved in the
IA32_PERF_GLOBAL_CTRL MSR must be 0 in the field for that register (see
Figure 18-15).
• If the “load IA32_PAT” VM-entry control is 1, the value of the field for the
IA32_PAT MSR must be one that could be written by WRMSR without fault at CPL
0. Specifically, each of the 8 bytes in the field must have one of the values 0 (UC),
1 (WC), 4 (WT), 5 (WP), 6 (WB), or 7 (UC-).
1. The bits corresponding to NW (bit 29) and CD (bit 30) are never checked because the values of
these bits are not changed by VM entry; see Section 22.3.2.1.
2. Software can determine a processor’s physical-address width by executing CPUID with
80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.