Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

22-12 Vol. 3
VM ENTRIES
— Bits 3:0 (Type) must be 3, indicating an expand-up read/write
accessed data segment.
— Bit 4 (S) must be 1.
— Bits 6:5 (DPL) must be 3.
— Bit 7 (P) must be 1.
— Bits 11:8 (reserved), bit 12 (software available), bit 13 (reserved/L),
bit 14 (D/B), bit 15 (G), bit 16 (unusable), and bits 31:17 (reserved)
must all be 0.
• If the guest will not be virtual-8086, the different sub-fields are
considered separately:
— Bits 3:0 (Type).
• CS. Bit 0 of the Type must be 1 (accessed) and bit 3 of the Type
must be 1 (code segment).
• SS. If SS is usable, the Type must be 3 or 7 (read/write,
accessed data segment).
• DS, ES, FS, GS. The following checks apply if the register is
usable:
— Bit 0 of the Type must be 1 (accessed).
— If bit 3 of the Type is 1 (code segment), then bit 1 of the
Type must be 1 (readable).
— Bit 4 (S). If the register is CS or if the register is usable, S must
be 1.
— Bits 6:5 (DPL).
• CS.
— If the Type is in the range 8–11 (non-conforming code
segment), the DPL must equal the RPL (bits 1:0) from the
selector field.
— If the Type is in the range 12–15 (conforming code
segment), the DPL cannot be greater than the RPL from the
selector field.
• SS. The DPL must equal the RPL from the selector field
• DS, ES, FS, GS. If the register is usable and the register’s Type is
in the range 0 – 11 (data segment or non-conforming code
segment), then the DPL cannot be less than the RPL from the
selector field.
— Bit 7 (P). If the register is CS or if the register is usable, P must be 1.
— Bits 11:8 (reserved). If the register is CS or if the register is usable,
these bits must all be 0.