Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

22-16 Vol. 3
VM ENTRIES
— Bit 2 (blocking by SMI) must be 0 if the processor is not in SMM.
— Bit 2 (blocking by SMI) must be 1 if the “entry to SMM” VM-entry control is 1.
— A processor may require bit 0 (blocking by STI) to be 0 if the valid bit (bit 31)
in the VM-entry interruption-information field is 1 and the interruption type
(bits 10:8) in that field has value 2, indicating NMI. Other processors may not
make this requirement.
— Bit 3 (blocking by NMI) must be 0 if the “virtual NMIs” VM-execution control
is 1, the valid bit (bit 31) in the VM-entry interruption-information field is 1,
and the interruption type (bits 10:8) in that field has value 2 (indicating
NMI).
NOTE
If the “virtual NMIs” VM-execution control is 0, there is no
requirement that bit 3 be 0 if the valid bit in the VM-entry
interruption-information field is 1 and the interruption type in that
field has value 2.
• Pending debug exceptions.
— Bits 11:4, bit 13, and bits 63:15 (bits 31:15 on processors that do not
support Intel 64 architecture) must be 0.
— The following checks are performed if any of the following holds: (1) the
interruptibility-state field indicates blocking by STI (bit 0 in that field is 1);
(2) the interruptibility-state field indicates blocking by MOV SS (bit 1 in that
field is 1); or (3) the activity-state field indicates HLT:
• Bit 14 (BS) must be 1 if the TF flag (bit 8) in the RFLAGS field is 1 and the
BTF flag (bit 1) in the IA32_DEBUGCTL field is 0.
• Bit 14 (BS) must be 0 if the TF flag (bit 8) in the RFLAGS field is 0 or the
BTF flag (bit 1) in the IA32_DEBUGCTL field is 1.
• VMCS link pointer. The following checks apply if the field contains a value other
than FFFFFFFF_FFFFFFFFH:
— Bits 11:0 must be 0.
— On processors that support Intel 64 architecture, bits beyond the processor’s
physical-address width must be 0.
1
On processors that do not support Intel
64 architecture, bits in the range 63:32 must be 0.
— The 32 bits located in memory referenced by the value of the field (as a
physical address) must contain the processor’s VMCS revision identifier (see
Section 20.2).
— If the processor is not in SMM or the “entry to SMM” VM-entry control is 1, the
field must not contain the current VMCS pointer.
1. Software can determine a processor’s physical-address width by executing CPUID with
80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.