Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

22-18 Vol. 3
VM ENTRIES
• Some state is determined by VM-entry controls.
• The page-directory pointers are loaded based on the values of certain control
registers.
This loading may be performed in any order and in parallel with the checking of VMCS
contents (see Section 22.3.1).
The loading of guest state is detailed in Section 22.3.2.1 to Section 22.3.2.4. These
sections reference VMCS fields that correspond to processor state. Unless otherwise
stated, these references are to fields in the guest-state area.
In addition to the state loading described in this section, VM entries may load MSRs
from the VM-entry MSR-load area (see Section 22.4). This loading occurs only after
the state loading described in this section and the checking of VMCS contents
described in Section 22.3.1.
22.3.2.1 Loading Guest Control Registers, Debug Registers, and MSRs
The following items describe how guest control registers, debug registers, and MSRs
are loaded on VM entry:
• CR0 is loaded from the CR0 field with the exception of the following bits, which
are never modified on VM entry: ET (bit 4); reserved bits 15:6, 17, and 28:19;
NW (bit 29) and CD (bit 30).
1
The values of these bits in the CR0 field are
ignored.
• CR3 and CR4 are loaded from the CR3 field and the CR4 field, respectively.
• If the “load debug controls” VM-execution control is 1, DR7 is loaded from the
DR7 field with the exception that bit 12 and bits 15:14 are always 0 and bit 10 is
always 1. The values of these bits in the DR7 field are ignored.
Note that the first processors to support the virtual-machine extensions
supported only the 1-setting of the “load debug controls” VM-execution control
and thus always loaded DR7 from the DR7 field.
• The following describes how some MSRs are loaded using fields in the guest-state
area:
— If the “load debug controls” VM-execution control is 1, the IA32_DEBUGCTL
MSR is loaded from the IA32_DEBUGCTL field. Note that the first processors
to support the virtual-machine extensions supported only the 1-setting of
this control and thus always loaded the IA32_DEBUGCTL MSR from the
IA32_DEBUGCTL field.
— The IA32_SYSENTER_CS MSR is loaded from the IA32_SYSENTER_CS field.
Since this field has only 32 bits, bits 63:32 of the MSR are cleared to 0.
— The IA32_SYSENTER_ESP and IA32_SYSENTER_EIP MSRs are loaded from
the IA32_SYSENTER_ESP field and the IA32_SYSENTER_EIP field, respec-
1. Bits 15:6, bit 17, and bit 28:19 of CR0 and CR0.ET are unchanged by executions of MOV to CR0.
Bits 15:6, bit 17, and bit 28:19 of CR0 are always 0 and CR0.ET is always 1.