Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 22-19
VM ENTRIES
tively. On processors that do not support Intel 64 architecture, these fields
have only 32 bits; bits 63:32 of the MSRs are cleared to 0.
— The following are performed on processors that support Intel 64 architecture:
• The MSRs FS.base and GS.base are loaded from the base-address fields
for FS and GS, respectively (see Section 22.3.2.2).
• If the “load IA32_EFER” VM-entry control is 0, the LMA and LME bits in the
IA32_EFER MSR are each loaded with the setting of the “IA-32e mode
guest” VM-entry control. See below for the case in which the “load
IA32_EFER” VM-entry control is 1
— If the “load IA32_PERF_GLOBAL_CTRL” VM-entry control is 1, the
IA32_PERF_GLOBAL_CTRL MSR is loaded from the
IA32_PERF_GLOBAL_CTRL field.
— If the “load IA32_PAT” VM-entry control is 1, the IA32_PAT MSR is loaded
from the IA32_PAT field.
— If the “load IA32_EFER” VM-entry control is 1, the IA32_EFER MSR is loaded
from the IA32_EFER field.
With the exception of FS.base and GS.base, any of these MSRs is subsequently
overwritten if it appears in the VM-entry MSR-load area. See Section 22.4.
• The SMBASE register is unmodified by all VM entries except those that return
from SMM.
22.3.2.2 Loading Guest Segment Registers and Descriptor-Table Registers
For each of CS, SS, DS, ES, FS, GS, TR, and LDTR, fields are loaded from the guest-
state area as follows:
• The unusable bit is loaded from the access-rights field. This bit can never be set
for TR (see Section 22.3.1.2). If it is set for one of the other registers, the
following apply:
— For each of CS, SS, DS, ES, FS, and GS, uses of the segment cause faults
(general-protection exception or stack-fault exception) outside 64-bit mode,
just as they would had the segment been loaded using a null selector. This bit
does not cause accesses to fault in 64-bit mode.
— If this bit is set for LDTR, uses of LDTR cause general-protection exceptions in
all modes, just as they would had LDTR been loaded using a null selector.
If this bit is clear for any of CS, SS, DS, ES, FS, GS, TR, and LDTR, a null
selector value does not cause a fault (general-protection exception or stack-
fault exception).
• TR. The selector, base, limit, and access-rights fields are loaded.
• CS.
— The following fields are always loaded: selector, base address, limit, and
(from the access-rights field) the L, D, and G bits.