Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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VM ENTRIES
• If the “virtualize APIC accesses” VM-execution control is 1 and event delivery
generates an access to the APIC-access page, that access may cause an APIC-
access VM exit (see Section 21.2) or, if the access is a VTPR access, be treated as
specified in Section 21.5.3.
1
If the event-delivery process does cause a VM exit, the processor state before the
VM exit is determined just as it would be had the injected event occurred during
normal execution in VMX non-root operation. If the injected event directly accesses a
task gate that cause a VM exit or if the first nested exception encountered causes a
VM exit, information about the injected event is saved in the IDT-vectoring informa-
tion field (see Section 23.2.3).
22.5.2 Injection of Pending MTF VM Exits
If the interruption type in the VM-entry interruption-information field is 7 (other
event) and the vector field is 0, VM entry causes an MTF VM exit to be pending on the
instruction boundary following VM entry. This is the case even if the “monitor trap
flag” VM-execution control is 0. See Section 21.7.2 for the treatment of pending MTF
VM exits.
22.6 SPECIAL FEATURES OF VM ENTRY
This section details a variety of features of VM entry. It uses the following termi-
nology: a VM entry is vectoring if the valid bit (bit 31) of the VM-entry interruption
information field is 1 and the interruption type in the field is 0 (external interrupt), 2
(non-maskable interrupt); 3 (hardware exception), 4 (software interrupt), 5 (privi-
leged software exception), or 6 (software exception).
22.6.1 Interruptibility State
The interruptibility-state field in the guest-state area (see Table 20-3) contains bits
that control blocking by STI, blocking by MOV SS, and blocking by NMI. This field
impacts event blocking after VM entry as follows:
• If the VM entry is vectoring, there is no blocking by STI or by MOV SS following
the VM entry, regardless of the contents of the interruptibility-state field.
• If the VM entry is not vectoring, the following apply:
— Events are blocked by STI if and only if bit 0 in the interruptibility-state field
is 1. Such blocking is cleared after the guest executes one instruction or
1. Note that “virtualize APIC accesses” is a secondary processor-based VM-execution control. If
bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if the
“virtualize APIC accesses” VM-execution control were 0. See Section 20.6.2.