Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 22-27
VM ENTRIES
incurs an exception (including a debug exception made pending by VM entry;
see Section 22.6.3).
— Events are blocked by MOV SS if and only if bit 1 in the interruptibility-state
field is 1. This may affect the treatment of pending debug exceptions; see
Section 22.6.3. Such blocking is cleared after the guest executes one
instruction or incurs an exception (including a debug exception made pending
by VM entry).
• The blocking of non-maskable interrupts (NMIs) is determined as follows:
— If the “virtual NMIs” VM-execution control is 0, NMIs are blocked if bit 3
(blocking by NMI) in the interruptibility-state field is 1. If the “NMI exiting”
VM-execution control is 0, such blocking remains in effect until IRET is
executed (even if the instruction generates a fault). If the “NMI exiting”
control is 1, such blocking remains in effect as long as the logical processor is
in VMX non-root operation.
— The following items describe the use of bit 3 (blocking by NMI) in the inter-
ruptibility-state field if the “virtual NMIs” VM-execution control is 1:
• The bit’s value does not affect the blocking of NMIs after VM entry. NMIs
are not blocked in VMX non-root operation (except for ordinary blocking
for other reasons, such as by the MOV SS instruction, the wait-for-SIPI
state, etc.)
• The bit’s value determines whether there is virtual-NMI blocking after
VM entry. If the bit is 1, virtual-NMI blocking is in effect after VM entry. If
the bit is 0, there is no virtual-NMI blocking after VM entry unless the
VM entry is injecting an NMI (see Section 22.5.1.1).
• Blocking of system-management interrupts (SMIs) is determined as follows:
— If the VM entry was not executed in system-management mode (SMM), SMI
blocking is unchanged by VM entry.
— If the VM entry was executed in SMM, SMIs are blocked after VM entry if and
only if the bit 2 in the interruptibility-state field is 1.
22.6.2 Activity State
The activity-state field in the guest-state area controls whether, after VM entry, the
logical processor is active or in one of the inactive states identified in Section 20.4.2.
The use of this field is determined as follows:
• If the VM entry is vectoring, the logical processor is in the active state after
VM entry. While the consistency checks described in Section 22.3.1.5 on the
activity-state field do apply in this case, the contents of the activity-state field do
not determine the activity state after VM entry.
• If the VM entry is not vectoring, the logical processor ends VM entry in the
activity state specified in the guest-state area. If VM entry ends with the logical
processor in an inactive activity state, the VM entry generates any special bus