Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 22-31
VM ENTRIES
22.6.7 VM Exits Induced by the TPR Shadow
If the “use TPR shadow” and “virtualize APIC accesses” VM-execution controls are
both 1, a VM exit occurs immediately after VM entry if the value of bits 3:0 of the TPR
threshold VM-execution control field is greater than the value of bits 7:4 in byte 80H
on the virtual-APIC page (see Section 20.6.8).
1
The following items detail the treatment of these VM exits:
• The VM exits are not blocked if RFLAGS.IF = 0 or by the setting of bits in the
interruptibility-state field in guest-state area.
• The VM exits follow event injection if such injection is specified for VM entry.
• VM exits caused by this control take priority over system-management interrupts
(SMIs), INIT signals, and lower priority events. They thus have priority over the
VM exits described in Section 22.6.5, Section 22.6.6, and Section 22.6.8, as well
as any interrupts or debug exceptions that may be pending at the time of
VM entry.
• These VM exits wake the logical processor if it just entered the HLT state as part
of a VM entry (see Section 22.6.2). They do not occur if the logical processor just
entered the shutdown state or the wait-for-SIPI state.
If such a VM exit is suppressed because the processor just entered the
shutdown state, it occurs after the delivery of any event that cause the logical
processor to leave the shutdown state while remaining in VMX non-root
operation (e.g., due to an NMI that occurs while the “NMI-exiting” VM-execution
control is 0).
• The basic exit reason is “TPR below threshold.”
22.6.8 Pending MTF VM Exits
As noted in Section 22.5.2, VM entry may cause an MTF VM exit to be pending imme-
diately after VM entry. The following items detail the treatment of these VM exits:
• System-management interrupts (SMIs), INIT signals, and higher priority events
take priority over these VM exits. These VM exits take priority over debug-trap
exceptions and lower priority events.
• These VM exits wake the logical processor if it just entered the HLT state because
of a VM entry (see Section 22.6.2). They do not occur if the logical processor just
entered the shutdown state or the wait-for-SIPI state.
1. Note that “virtualize APIC accesses” is a secondary processor-based VM-execution control. If
bit 31 of the primary processor-based VM-execution controls is 0, VM entry functions as if the
“virtualize APIC accesses” VM-execution control were 0. See Section 20.6.2.