Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

23-2 Vol. 3
VM EXITS
causes a VM exit directly if the “external-interrupt exiting” VM-execution control
is 1. A start-up IPI (SIPI) that arrives while a logical processor is in the wait-for-
SIPI activity state causes a VM exit directly. INIT signals that arrive while the
processor is not in the wait-for-SIPI activity state cause VM exits directly.
• An exception, NMI, external interrupt, or software interrupt causes a VM exit
indirectly if it does not do so directly but delivery of the event causes a nested
exception, double fault, task switch, APIC access (see Section 21.2), EPT
violation, or EPT misconfiguration that causes a VM exit.
• An event results in a VM exit if it causes a VM exit (directly or indirectly).
The following bullets detail when architectural state is and is not updated in response
to VM exits:
• If an event causes a VM exit directly, it does not update architectural state as it
would have if it had it not caused the VM exit:
— A debug exception does not update DR6, DR7.GD, or IA32_DEBUGCTL.LBR.
(Information about the nature of the debug exception is saved in the exit
qualification field.)
— A page fault does not update CR2. (The linear address causing the page fault
is saved in the exit-qualification field.)
— An NMI causes subsequent NMIs to be blocked, but only after the VM exit
completes.
— An external interrupt does not acknowledge the interrupt controller and the
interrupt remains pending, unless the “acknowledge interrupt on exit”
VM-exit control is 1. In such a case, the interrupt controller is acknowledged
and the interrupt is no longer pending.
— The flags L0 – L3 in DR7 (bit 0, bit 2, bit 4, and bit 6) are not cleared when a
task switch causes a VM exit.
— If a task switch causes a VM exit, none of the following are modified by the
task switch: old task-state segment (TSS); new TSS; old TSS descriptor; new
TSS descriptor; RFLAGS.NT
1
; or the TR register.
— No last-exception record is made if the event that would do so directly causes
a VM exit.
— If a machine-check exception causes a VM exit directly, this does not prevent
machine-check MSRs from being updated. These are updated by the machine
check itself and not the resulting machine-check exception.
1. This chapter uses the notation RAX, RIP, RSP, RFLAGS, etc. for processor registers because most
processors that support VMX operation also support Intel 64 architecture. For processors that do
not support Intel 64 architecture, this notation refers to the 32-bit forms of those registers
(EAX, EIP, ESP, EFLAGS, etc.). In a few places, notation such as EAX is used to refer specifically to
lower 32 bits of the indicated register.