Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

23-6 Vol. 3
VM EXITS
— For a debug exception, the exit qualification contains information about the
debug exception. The information has the format given in Table 23-1.
— For a page-fault exception, the exit qualification contains the linear address
that caused the page fault. On processors that support Intel 64 architecture,
bits 63:32 are cleared if the logical processor was not in 64-bit mode before
the VM exit.
— For a start-up IPI (SIPI), the exit qualification contains the SIPI vector
information in bits 7:0. Bits 63:8 of the exit qualification are cleared to 0.
— For a task switch, the exit qualification contains details about the task switch,
encoded as shown in Table 23-2.
Table 23-1. Exit Qualification for Debug Exceptions
Bit Position(s) Contents
3:0 B3 – B0. When set, each of these bits indicates that the corresponding
breakpoint condition was met. Any of these bits may be set even if its
corresponding enabling bit in DR7 is not set.
12:4 Reserved (cleared to 0).
13 BD. When set, this bit indicates that the cause of the debug exception is
“debug register access detected.”
14 BS. When set, this bit indicates that the cause of the debug exception is
either the execution of a single instruction (if RFLAGS.TF = 1 and
IA32_DEBUGCTL.BTF = 0) or a taken branch (if
RFLAGS.TF = DEBUGCTL.BTF = 1).
63:15 Reserved (cleared to 0). Bits 63:32 exist only on processors that
support Intel 64 architecture.
Table 23-2. Exit Qualification for Task Switch
Bit Position(s) Contents
15:0 Selector of task-state segment (TSS) to which the guest attempted to switch
29:16 Reserved (cleared to 0)
31:30 Source of task switch initiation:
0: CALL instruction
1: IRET instruction
2: JMP instruction
3: Task gate in IDT