Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

23-10 Vol. 3
VM EXITS
— For MWAIT, the exit qualification contains a value that indicates whether
address-range monitoring hardware was armed. The exit qualification is set
either to 0 (if address-range monitoring hardware is not armed) or to 1 (if
address-range monitoring hardware is armed).
— For an APIC-access VM exit resulting from a linear access or a guest-physical
access to the APIC-access page (see Section 21.2.1 and Section 21.2.1), the
exit qualification contains information about the access and has the format
given in Table 23-6.
1
5 REP prefixed (0 = not REP; 1 = REP)
6 Operand encoding (0 = DX, 1 = immediate)
15:7 Reserved (cleared to 0)
31:16 Port number (as specified in DX or in an immediate operand)
63:32 Reserved (cleared to 0). These bits exist only on processors that support Intel
64 architecture.
Table 23-6. Exit Qualification for APIC-Access VM Exits from Linear Accesses and
Guest-Physical Accesses
Bit Position(s) Contents
11:0 • If the APIC-access VM exit is due to a linear access, the offset of access
within the APIC page.
• Undefined if the APIC-access VM exit is due a guest-physical access
15:12 Access type:
0 = linear access for a data read during instruction execution
1 = linear access for a data write during instruction execution
2 = linear access for an instruction fetch
3 = linear access (read or write) during event delivery
10 = guest-physical access during event delivery
15 = guest-physical access for an instruction fetch or during instruction
execution
Other values not used
63:16 Reserved (cleared to 0). Bits 63:32 exist only on processors that support
Intel 64 architecture.
Table 23-5. Exit Qualification for I/O Instructions (Contd.)
Bit Position(s) Contents