Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

23-32 Vol. 3
VM EXITS
— If the “enable EPT” VM-execution control is 0 or the logical processor was not
using PAE paging at the time of the VM exit, the values saved are undefined.
23.4 SAVING MSRS
After processor state is saved to the guest-state area, values of MSRs may be stored
into the VM-exit MSR-store area (see Section 20.7.2). Specifically each entry in that
area (up to the number specified in the VM-exit MSR-store count) is processed in
order by storing the value of the MSR indexed by bits 31:0 (as they would be read by
RDMSR) into bits 127:64. Processing of an entry fails in either of the following cases:
• The value of bits 31:8 is 000008H, meaning that the indexed MSR is one that
allows access to an APIC register when the local APIC is in x2APIC mode.
• The value of bits 31:0 indicates an MSR that can be read only in system-
management mode (SMM) and the VM exit will not end in SMM.
• The value of bits 31:0 indicates an MSR that cannot be saved on VM exits for
model-specific reasons. A processor may prevent certain MSRs (based on the
value of bits 31:0) from being stored on VM exits, even if they can normally be
read by RDMSR. Such model-specific behavior is documented in Appendix B.
• Bits 63:32 of the entry are not all 0.
• An attempt to read the MSR indexed by bits 31:0 would cause a general-
protection exception if executed via RDMSR with CPL = 0.
A VMX abort occurs if processing fails for any entry. See Section 23.7.
23.5 LOADING HOST STATE
Processor state is updated on VM exits in the following ways:
• Some state is loaded from or otherwise determined by the contents of the host-
state area.
• Some state is determined by VM-exit controls.
• Some state is established in the same way on every VM exit.
• The page-directory pointers are loaded based on the values of certain control
registers.
This loading may be performed in any order.
On processors that support Intel 64 architecture, the full values of each 64-bit field
loaded (for example, the base address for GDTR) is loaded regardless of the mode of
the logical processor before and after the VM exit.
The loading of host state is detailed in Section 23.5.1 to Section 23.5.5. These
sections reference VMCS fields that correspond to processor state. Unless otherwise
stated, these references are to fields in the host-state area.