Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

23-34 Vol. 3
VM EXITS
• The MSRs FS.base and GS.base are loaded from the base-address fields
for FS and GS, respectively (see Section 23.5.2).
• The LMA and LME bits in the IA32_EFER MSR are each loaded with the
setting of the “host address-space size” VM-exit control.
— If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, the
IA32_PERF_GLOBAL_CTRL MSR is loaded from the
IA32_PERF_GLOBAL_CTRL field.
— If the “load IA32_PAT” VM-exit control is 1, the IA32_PAT MSR is loaded from
the IA32_PAT field.
— If the “load IA32_EFER” VM-exit control is 1, the IA32_EFER MSR is loaded
from the IA32_EFER field.
With the exception of FS.base and GS.base, any of these MSRs is subsequently
overwritten if it appears in the VM-exit MSR-load area. See Section 23.6.
23.5.2 Loading Host Segment and Descriptor-Table Registers
Each of the registers CS, SS, DS, ES, FS, GS, and TR is loaded as follows (see below
for the treatment of LDTR):
• The selector is loaded from the selector field. The segment is unusable if its
selector is loaded with zero. Note that the checks specified Section 22.3.1.2 limit
the selector values that may be loaded. In particular, CS and TR are never loaded
with zero and are thus never unusable. SS can be loaded with zero only on
processors that support Intel 64 architecture and only if the VM exit is to 64-bit
mode (64-bit mode allows use of segments marked unusable).
• The base address is set as follows:
— CS. Cleared to zero.
— SS, DS, and ES. Undefined if the segment is unusable; otherwise, cleared to
zero.
— FS and GS. Undefined (but, on processors that support Intel 64 architecture,
canonical) if the segment is unusable and the VM exit is not to 64-bit mode;
otherwise, loaded from the base-address field. Note that, on processors that
support Intel 64 architecture, the values loaded for base addresses for FS and
GS are also manifest in the FS.base and GS.base MSRs.
— TR. Loaded from the host-state area.
• The segment limit is set as follows:
— CS. Set to FFFFFFFFH (corresponding to a descriptor limit of FFFFFH and a G-
bit setting of 1).
— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set
to FFFFFFFFH.
— TR. Set to 00000067H.