Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-27
DEBUGGING AND PERFORMANCE MONITORING
• BTINT (branch trace interrupt) flag (bits 4) — When set, the BTS facilities
generate an interrupt when the BTS buffer is full. When clear, BTMs are logged to
the BTS buffer in a circular fashion. See Section 18.7.8, “Branch Trace Store (BTS).”
• BTS_OFF_OS (disable ring 0 branch trace store) flag (bit 5) — When set,
enables the BTS facilities to skip sending/logging CPL_0 BTMs to the memory-
resident BTS buffer. See Section 18.7.1, “CPL-Qualified Branch Trace
Mechanism.”
• BTS_OFF_USR (disable ring 0 branch trace store) flag (bit 6) — When set,
enables the BTS facilities to skip sending/logging non-CPL_0 BTMs to the
memory-resident BTS buffer. See Section 18.7.1, “CPL-Qualified Branch Trace
Mechanism.”
18.7.3 LBR Stack for Processors Based on Intel NetBurst
Microarchitecture
The LBR stack is made up of LBR MSRs that are treated by the processor as a circular
stack. The TOS pointer (MSR_LASTBRANCH_TOS MSR) points to the LBR MSR (or
LBR MSR pair) that contains the most recent (last) branch record placed on the stack.
Prior to placing a new branch record on the stack, the TOS is incremented by 1. When
the TOS pointer reaches it maximum value, it wraps around to 0. See Table 18-7 and
Figure 18-6.
The registers in the LBR MSR stack and the MSR_LASTBRANCH_TOS MSR are read-
only and can be read using the RDMSR instruction.
Figure 18-7 shows the layout of a branch record in an LBR MSR (or MSR pair). Each
branch record consists of two linear addresses, which represent the “from” and “to”
instruction pointers for a branch, interrupt, or exception. The contents of the from
and to addresses differ, depending on the source of the branch:
• Taken branch — If the record is for a taken branch, the “from” address is the
address of the branch instruction and the “to” address is the target instruction of
the branch.
• Interrupt — If the record is for an interrupt, the “from” address the return
instruction pointer (RIP) saved for the interrupt and the “to” address is the
address of the first instruction in the interrupt handler routine. The RIP is the
linear address of the next instruction to be executed upon returning from the
interrupt handler.
• Exception — If the record is for an exception, the “from” address is the linear
address of the instruction that caused the exception to be generated and the “to”
address is the address of the first instruction in the exception handler routine.