Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

24-12 Vol. 3
SUPPORT FOR ADDRESS TRANSLATION
For an access to a guest-physical address, determination of whether an EPT miscon-
figuration or an EPT violation occurs is based on an iterative process:
1
1. An EPT paging-structure entry is read (initially, this is an EPT PML4 entry):
a. If the entry is not present (bits 2:0 are all 0), an EPT violation occurs.
b. If the entry is present but its contents are not configured properly (see
Section 24.2.4.1), an EPT misconfiguration occurs.
c. If the entry is present and its contents are configured properly, operation
depends on whether the entry references another EPT paging structure
(whether it is an EPT PDE with bit 7 set to 1 or an EPT PTE):
i) If the entry does references another EPT paging structure, an entry from
that structure is accessed; step 1 is executed for that other entry.
ii) Otherwise, the entry is used to produce the ultimate physical address
(the translation of the original guest-physical address); step 2 is
executed.
2. Once the ultimate physical address is determined, the privileges determined by
the EPT paging-structure entries are evaluated:
a. If the access to the guest-physical address is not allowed by these privileges
(see Section 24.2.4.2), an EPT violation occurs.
b. If the access to the guest-physical address is allowed by these privileges,
memory is accessed using the ultimate physical address.
The translation of a linear address is also an iterative process, with the processor first
accessing an entry in the guest paging structure referenced by the guest-physical
address in CR3, then accessing an entry in another guest paging structure referenced
by the guest-physical address in the first guest paging-structure entry, etc. Each
guest-physical address is itself translated using EPT and may cause an EPT-induced
VM exit. The following items detail how page faults and EPT-induced VM exits are
recognized during this iterative process:
1. An attempt is made to access a guest paging-structure entry with a guest-
physical address (initially, the address is derived from the one in CR3).
a. If the access fails because of an EPT misconfiguration or an EPT violation (see
above), an EPT-induced VM exit occurs.
b. If the access does not cause an EPT-induced VM exit, bit 0 (the present flag)
of the entry is consulted:
i) If the present flag is 0 or any reserved bit is set, a page fault occurs.
ii) If the present flag is 1, no reserved bit is set, operation depends on
whether the entry references another guest paging structure (whether it
is a guest PDE with PS = 1 or a guest PTE):
1. This is a simplification of the more detailed description given in Section 24.2.2.