Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

24-14 Vol. 3
SUPPORT FOR ADDRESS TRANSLATION
24.2.5.2 Memory Type Used for Translated Guest-Physical Addresses
The effective memory type of a memory access using a guest-physical address (an
access that is translated using EPT) is the memory type that is used to access
memory. The effective memory type is based on the value of bit 30 (cache
disable—CD) in control register CR0; the last EPT paging-structure entry used to
translate the guest-physical address (either an EPT PDE with bit 7 set to 1 or an EPT
PTE); and the PAT memory type (see below):
• The PAT memory type is the memory type selected from the IA32_PAT MSR as
specified in Section 10.12.3, “Selecting a Memory Type from the PAT”.
1
• The EPT memory type is specified in bits 5:3 of the last EPT paging-structure
entry: 0= UC; 1= WC; 4= WT; 5= WP; and 6= WB. Other values are reserved
and will cause an EPT misconfiguration (see Section 24.2.4).
• If CR0.CD = 0, the effective memory type depends upon the value of bit 6 of the
last EPT paging-structure entry:
— If the value is 0, the effective memory type is the combination of the EPT
memory type and the PAT memory type specified in Table 10-7 in Section
10.5.2.2, using the EPT memory type in place of the MTRR memory type.
— If the value is 1, the memory type used for the access is the EPT memory
type. The PAT memory type is ignored.
• If CR0.CD = 1, the effective memory type is UC.
Note that the MTRRs have no effect on the memory type used for an access to a
guest-physical address.
24.3 CACHING TRANSLATION INFORMATION
Processors supporting Intel
®
64 and IA-32 architectures may accelerate the
address-translation process by caching on the processor data from the structures in
memory that control that process. Such caching is discussed in the application note
“TLBs, Paging-Structure Caches, and Their Invalidation.” This section describes how
this caching interacts with the VMX architecture.
The VPID and EPT features of the architecture for VMX operation augment this
caching architecture. EPT defines the guest-physical address space and defines
translations to that address space (from the linear-address space) and from that
address space (to the physical-address space). Both features control the ways in
1. Table 10-11 in Section 10.12.3, “Selecting a Memory Type from the PAT” illustrates how the PAT
memory type is selected based on the values of the PAT, PCD, and PWT bits in a page-table entry
(or page-directory entry with PS = 1). For accesses to a guest paging-structure entry X, the PAT
memory type is selected from the table by using a value of 0 for the PAT bit with the values of
PCD and PWT from the paging-structure entry Y that references X (or from CR3 if X is in the root
paging structure).