Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

25-4 Vol. 3
SYSTEM MANAGEMENT
An SMI has a greater priority than debug exceptions and external interrupts. Thus, if
an NMI, maskable hardware interrupt, or a debug exception occurs at an instruction
boundary along with an SMI, only the SMI is handled. Subsequent SMI requests are
not acknowledged while the processor is in SMM. The first SMI interrupt request that
occurs while the processor is in SMM (that is, after SMM has been acknowledged to
external hardware) is latched and serviced when the processor exits SMM with the
RSM instruction. The processor will latch only one SMI while in SMM.
See Section 25.5 for a detailed description of the execution environment when in
SMM.
25.3.2 Exiting From SMM
The only way to exit SMM is to execute the RSM instruction. The RSM instruction is
only available to the SMI handler; if the processor is not in SMM, attempts to execute
the RSM instruction result in an invalid-opcode exception (#UD) being generated.
The RSM instruction restores the processor’s context by loading the state save image
from SMRAM back into the processor’s registers. The processor then returns an
SMIACK transaction on the system bus and returns program control back to the
interrupted program.
Upon successful completion of the RSM instruction, the processor signals external
hardware that SMM has been exited. For the P6 family processors, an SMI acknowl-
edge transaction is generated on the system bus and the multiplexed status signal
EXF4 is no longer generated on bus cycles. For the Pentium and Intel486 processors,
the SMIACT# pin is deserted.
If the processor detects invalid state information saved in the SMRAM, it enters the
shutdown state and generates a special bus cycle to indicate it has entered shutdown
state. Shutdown happens only in the following situations:
• A reserved bit in control register CR4 is set to 1 on a write to CR4. This error
should not happen unless SMI handler code modifies reserved areas of the
SMRAM saved state map (see Section 25.4.1). Note that CR4 is saved in the state
map in a reserved location and cannot be read or modified in its saved state.
• An illegal combination of bits is written to control register CR0, in particular PG
set to 1 and PE set to 0, or NW set to 1 and CD set to 0.
• (For the Pentium and Intel486 processors only.) If the address stored in the
SMBASE register when an RSM instruction is executed is not aligned on a
32-KByte boundary. This restriction does not apply to the P6 family processors.
In the shutdown state, Intel processors stop executing instructions until a RESET#,
INIT# or NMI# is asserted. While Pentium family processors recognize the SMI#
signal in shutdown state, P6 family and Intel486 processors do not. Intel does not
support using SMI# to recover from shutdown states for any processor family; the
response of processors in this circumstance is not well defined. On Pentium 4 and
later processors, shutdown will inhibit INTR and A20M but will not change any of the