Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 25-11
SYSTEM MANAGEMENT
25.4.2 SMRAM Caching
An IA-32 processor does not automatically write back and invalidate its caches before
entering SMM or before exiting SMM. Because of this behavior, care must be taken in
the placement of the SMRAM in system memory and in the caching of the SMRAM to
prevent cache incoherence when switching back and forth between SMM and
protected mode operation. Either of the following three methods of locating the
SMRAM in system memory will guarantee cache coherency:
• Place the SRAM in a dedicated section of system memory that the operating
system and applications are prevented from accessing. Here, the SRAM can be
designated as cacheable (WB, WT, or WC) for optimum processor performance,
without risking cache incoherence when entering or exiting SMM.
• Place the SRAM in a section of memory that overlaps an area used by the
operating system (such as the video memory), but designate the SMRAM as
uncacheable (UC). This method prevents cache access when in SMM to maintain
cache coherency, but the use of uncacheable memory reduces the performance
of SMM code.
• Place the SRAM in a section of system memory that overlaps an area used by the
operating system and/or application code, but explicitly flush (write back and
invalidate) the caches upon entering and exiting SMM mode. This method
7E94H IDT Base (lower 32 bits) No
7E90H GDT Limit No
7E8CH GDT Base (lower 32 bits) No
7E8BH - 7E44H Reserved No
7E40H CR4 No
7E3FH - 7DF0H Reserved No
7DE8H IO_EIP Yes
7DE7H - 7DDCH Reserved No
7DD8H IDT Base (Upper 32 bits) No
7DD4H LDT Base (Upper 32 bits) No
7DD0H GDT Base (Upper 32 bits) No
7DCFH - 7C00H Reserved No
NOTE:
1. The two most significant bytes are reserved.
Table 25-3. SMRAM State Save Map for Intel 64 Architecture (Contd.)
Offset
(Added to SMBASE +
8000H)
Register Writable?