Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

25-12 Vol. 3
SYSTEM MANAGEMENT
maintains cache coherency, but the incurs the overhead of two complete cache
flushes.
For Pentium 4, Intel Xeon, and P6 family processors, a combination of the first two
methods of locating the SMRAM is recommended. Here the SMRAM is split between
an overlapping and a dedicated region of memory. Upon entering SMM, the SMRAM
space that is accessed overlaps video memory (typically located in low memory).
This SMRAM section is designated as UC memory. The initial SMM code then jumps to
a second SMRAM section that is located in a dedicated region of system memory
(typically in high memory). This SMRAM section can be cached for optimum
processor performance.
For systems that explicitly flush the caches upon entering SMM (the third method
described above), the cache flush can be accomplished by asserting the FLUSH# pin
at the same time as the request to enter SMM (generally initiated by asserting the
SMI# pin). The priorities of the FLUSH# and SMI# pins are such that the FLUSH# is
serviced first. To guarantee this behavior, the processor requires that the following
constraints on the interaction of FLUSH# and SMI# be met. In a system where the
FLUSH# and SMI# pins are synchronous and the set up and hold times are met, then
the FLUSH# and SMI# pins may be asserted in the same clock. In asynchronous
systems, the FLUSH# pin must be asserted at least one clock before the SMI# pin to
guarantee that the FLUSH# pin is serviced first.
Upon leaving SMM (for systems that explicitly flush the caches), the WBINVD instruc-
tion should be executed prior to leaving SMM to flush the caches.
NOTES
In systems based on the Pentium processor that use the FLUSH# pin
to write back and invalidate cache contents before entering SMM, the
processor will prefetch at least one cache line in between when the
Flush Acknowledge cycle is run and the subsequent recognition of
SMI# and the assertion of SMIACT#.
It is the obligation of the system to ensure that these lines are not
cached by returning KEN# inactive to the Pentium processor.
25.5 SMI HANDLER EXECUTION ENVIRONMENT
After saving the current context of the processor, the processor initializes its core
registers to the values shown in Table 25-4. Upon entering SMM, the PE and PG flags
in control register CR0 are cleared, which places the processor is in an environment
similar to real-address mode. The differences between the SMM execution environ-
ment and the real-address mode execution environment are as follows:
• The addressable SMRAM address space ranges from 0 to FFFFFFFFH (4 GBytes).
(The physical address extension (enabled with the PAE flag in control register
CR4) is not supported in SMM.)
• The normal 64-KByte segment limit for real-address mode is increased to
4GBytes.