Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-31
DEBUGGING AND PERFORMANCE MONITORING
18.7.8.2 Setting Up the DS Save Area
To save branch records with the BTS buffer, the DS save area must first be set up in
memory as described in the following procedure. See Section 18.7.8.3, “Setting Up
the BTS Buffer,” and Section 18.18.8.3, “Setting Up the PEBS Buffer,” for instructions
for setting up a BTS buffer and/or a PEBS buffer, respectively, in the DS save area:
1. Create the DS buffer management information area in memory (see Section
18.18.5, “DS Save Area,” and Section 18.18.5.1, “DS Save Area and IA-32e Mode
Operation”). Also see the additional notes in this section.
2. Write the base linear address of the DS buffer management area into the
IA32_DS_AREA MSR.
3. Set up the performance counter entry in the xAPIC LVT for fixed delivery and
edge sensitive. See Section 9.6.1, “Local Vector Table.”
4. Establish an interrupt handler in the IDT for the vector associated with the
performance counter entry in the xAPIC LVT.
5. Write an interrupt service routine to handle the interrupt. See Section 18.7.8.5,
“Writing the DS Interrupt Service Routine.”
The following restrictions should be applied to the DS save area.
• The three DS save area sections should be allocated from a non-paged pool, and
marked accessed and dirty. It is the responsibility of the operating system to
keep the pages that contain the buffer present and to mark them accessed and
dirty. The implication is that the operating system cannot do “lazy” page-table
entry propagation for these pages.
• The DS save area can be larger than a page, but the pages must be mapped to
contiguous linear addresses. The buffer may share a page, so it need not be
aligned on a 4-KByte boundary. For performance reasons, the base of the buffer
must be aligned on a doubleword boundary and should be aligned on a cache line
boundary.
• It is recommended that the buffer size for the BTS buffer and the PEBS buffer be
an integer multiple of the corresponding record sizes.
• The precise event records buffer should be large enough to hold the number of
precise event records that can occur while waiting for the interrupt to be
serviced.
• The DS save area should be in kernel space. It must not be on the same page as
code, to avoid triggering self-modifying code actions.
• There are no memory type restrictions on the buffers, although it is
recommended that the buffers be designated as WB memory type for
performance considerations.
• Either the system must be prevented from entering A20M mode while DS save
area is active, or bit 20 of all addresses within buffer bounds must be 0.