Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

25-14 Vol. 3
SYSTEM MANAGEMENT
Maskable hardware interrupts, exceptions, NMI interrupts, SMI interrupts, A20M
interrupts, single-step traps, breakpoint traps, and INIT operations are inhibited
when the processor enters SMM. Maskable hardware interrupts, exceptions, single-
step traps, and breakpoint traps can be enabled in SMM if the SMM execution envi-
ronment provides and initializes an interrupt table and the necessary interrupt and
exception handlers (see Section 25.6).
25.6 EXCEPTIONS AND INTERRUPTS WITHIN SMM
When the processor enters SMM, all hardware interrupts are disabled in the following
manner:
• The IF flag in the EFLAGS register is cleared, which inhibits maskable hardware
interrupts from being generated.
• The TF flag in the EFLAGS register is cleared, which disables single-step traps.
• Debug register DR7 is cleared, which disables breakpoint traps. (This action
prevents a debugger from accidentally breaking into an SMM handler if a debug
breakpoint is set in normal address space that overlays code or data in SMRAM.)
• NMI, SMI, and A20M interrupts are blocked by internal SMM logic. (See Section
25.8 for more information about how NMIs are handled in SMM.)
Software-invoked interrupts and exceptions can still occur, and maskable hardware
interrupts can be enabled by setting the IF flag. Intel recommends that SMM code be
written in so that it does not invoke software interrupts (with the INT n, INTO, INT 3,
or BOUND instructions) or generate exceptions.
If the SMM handler requires interrupt and exception handling, an SMM interrupt table
and the necessary exception and interrupt handlers must be created and initialized
from within SMM. Until the interrupt table is correctly initialized (using the LIDT
instruction), exceptions and software interrupts will result in unpredictable processor
behavior.
The following restrictions apply when designing SMM interrupt and exception-
handling facilities:
• The interrupt table should be located at linear address 0 and must contain real-
address mode style interrupt vectors (4 bytes containing CS and IP).
• Due to the real-address mode style of base address formation, an interrupt or
exception cannot transfer control to a segment with a base address of more that
20 bits.
• An interrupt or exception cannot transfer control to a segment offset of more
than 16 bits (64 KBytes).
• When an exception or interrupt occurs, only the 16 least-significant bits of the
return address (EIP) are pushed onto the stack. If the offset of the interrupted
procedure is greater than 64 KBytes, it is not possible for the interrupt/exception
handler to return control to that procedure. (One solution to this problem is for a
handler to adjust the return address on the stack.)