Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 25-15
SYSTEM MANAGEMENT
• The SMBASE relocation feature affects the way the processor will return from an
interrupt or exception generated while the SMI handler is executing. For
example, if the SMBASE is relocated to above 1 MByte, but the exception
handlers are below 1 MByte, a normal return to the SMI handler is not possible.
One solution is to provide the exception handler with a mechanism for calculating
a return address above 1 MByte from the 16-bit return address on the stack, then
use a 32-bit far call to return to the interrupted procedure.
• If an SMI handler needs access to the debug trap facilities, it must insure that an
SMM accessible debug handler is available and save the current contents of
debug registers DR0 through DR3 (for later restoration). Debug registers DR0
through DR3 and DR7 must then be initialized with the appropriate values.
• If an SMI handler needs access to the single-step mechanism, it must insure that
an SMM accessible single-step handler is available, and then set the TF flag in the
EFLAGS register.
• If the SMI design requires the processor to respond to maskable hardware
interrupts or software-generated interrupts while in SMM, it must ensure that
SMM accessible interrupt handlers are available and then set the IF flag in the
EFLAGS register (using the STI instruction). Software interrupts are not blocked
upon entry to SMM, so they do not need to be enabled.
25.7 MANAGING SYNCHRONOUS AND ASYNCHRONOUS
SYSTEM MANAGEMENT INTERRUPTS
When coding for a multiprocessor system or a system with Intel HT Technology, it
was not always possible for an SMI handler to distinguish between a synchronous
SMI (triggered during an I/O instruction) and an asynchronous SMI. To facilitate the
discrimination of these two events, incremental state information has been added to
the SMM state save map.
Processors that have an SMM revision ID of 30004H or higher have the incremental
state information described below.
25.7.1 I/O State Implementation
Within the extended SMM state save map, a bit (IO_SMI) is provided that is set only
when an SMI is either taken immediately after a successful I/O instruction or is taken
after a successful iteration of a REP I/O instruction (note that the successful notion
pertains to the processor point of view; not necessarily to the corresponding platform
function). When set, the IO_SMI bit provides a strong indication that the corre-
sponding SMI was synchronous. In this case, the SMM State Save Map also supplies
the port address of the I/O operation. The IO_SMI bit and the I/O Port Address may
be used in conjunction with the information logged by the platform to confirm that
the SMI was indeed synchronous.