Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

25-36 Vol. 3
SYSTEM MANAGEMENT
25.15.6 Activating the Dual-Monitor Treatment
The dual-monitor treatment may be enabled by SMM code as described in Section
25.15.5. The dual-monitor treatment is activated only if it is enabled and only by the
executive monitor. The executive monitor activates the dual-monitor treatment by
executing VMCALL in VMX root operation.
When VMCALL activates the dual-monitor treatment, it causes an SMM VM exit.
Differences between this SMM VM exit and other SMM VM exits are discussed in
Sections 25.15.6.1 through 25.15.6.5. See also “VMCALL—Call to VM Monitor” in
Chapter 6 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B.
25.15.6.1 Initial Checks
An execution of VMCALL attempts to activate the dual-monitor treatment if (1) the
processor supports the dual-monitor treatment;
1
(2) the logical processor is in VMX
root operation; (3) the logical processor is outside SMM and the valid bit is set in the
IA32_SMM_MONITOR_CTL MSR; (4) the logical processor is not in virtual-8086
mode and not in compatibility mode; (5) CPL = 0; and (6) the dual-monitor treat-
ment is not active.
The VMCS that manages SMM VM exit caused by this VMCALL is the current VMCS
established by the executive monitor. The VMCALL performs the following checks on
the current VMCS in the order indicated:
1. There must be a current VMCS pointer.
2. The launch state of the current VMCS must be clear.
3. The VM-exit control fields must be valid:
— Reserved bits in the VM-exit controls must be set properly. Software may
consult the VMX capability MSR IA32_VMX_EXIT_CTLS to determine the
proper settings (see Appendix G.4).
— The following checks are performed for the VM-exit MSR-store address if the
VM-exit MSR-store count field is non-zero:
• The lower 4 bits of the VM-exit MSR-store address must be 0. On
processors that support Intel 64 architecture, the address should not set
any bits beyond the processor’s physical-address width.
2
On processors
that do not support Intel 64 architecture, the address should not set any
bits in the range 63:32.
• On processors that support Intel 64 architecture, the address of the last
byte in the VM-exit MSR-store area should not set any bits beyond the
1. Software should consult the VMX capability MSR IA32_VMX_BASIC (see Appendix G.1) to deter-
mine whether the dual-monitor treatment is supported.
2. Software can determine a processor’s physical-address width by executing CPUID with
80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX.