Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 26-3
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
Before entering VMX operation, the host VMM allocates a VMXON region. A VMM can
host several virtual machines and have many VMCSs active under its management.
A unique VMCS region is required for each virtual machine; a VMXON region is
required for the VMM itself.
A VMM determines the VMCS region size by reading IA32_VMX_BASIC MSR; it
creates VMCS regions of this size using a 4-KByte-aligned area of physical memory.
Each VMCS region needs to be initialized with a VMCS revision identifier (at byte
offset 0) identical to the revision reported by the processor in the VMX capability
MSR.
NOTE
Software must not read or write directly to the VMCS data region as
the format is not architecturally defined. Consequently, we
recommend that the VMM remove any linear-address mappings to
VMCS regions before loading.
System software does not need to do special preparation to the VMXON region before
entering into VMX operation. The address of the VMXON region for the VMM is
provided as an operand to VMXON instruction. Once in VMX root operation, the VMM
needs to prepare data fields in the VMCS that control the execution of a VM upon a
VM entry. The VMM can make a VMCS the current VMCS by using the VMPTRLD
instruction. VMCS data fields must be read or written only through VMREAD and
VMWRITE commands respectively.
Every component of the VMCS is identified by a 32-bit encoding that is provided as
an operand to VMREAD and VMWRITE. Appendix H provides the encodings. A VMM
must properly initialize all fields in a VMCS before using the current VMCS for VM
entry.
A VMCS is referred to as a controlling VMCS if it is the current VMCS on a logical
processor in VMX non-root operation. A current VMCS for controlling a logical
processor in VMX non-root operation may be referred to as a working VMCS if the
logical processor is not in VMX non-root operation. The relationship of active, current
(i.e. working) and controlling VMCS during VMX operation is shown in Figure 26-1.
The VMX capability MSR IA32_VMX_BASIC reports the memory type used by the
processor for accessing a VMCS or any data structures referenced through pointers in
the VMCS. Software must maintain the VMCS structures in cache-coherent memory.
Software must always map the regions hosting the I/O bitmaps, MSR bitmaps, VM-
exit MSR-store area, VM-exit MSR-load area, and VM-entry MSR-load area to the
write-back (WB) memory type. Mapping these regions to uncacheable (UC) memory
type is supported, but strongly discouraged due to negative impact on performance.