Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

26-6 Vol. 3
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
• Enable VMX operation by setting CR4.VMXE = 1. Ensure the resultant CR4 value
supports all the CR4 fixed bits reported in the IA32_VMX_CR4_FIXED0 and
IA32_VMX_CR4_FIXED1 MSRs.
• Ensure that the IA32_FEATURE_CONTROL MSR (MSR index 3AH) has been
properly programmed and that its lock bit is set (Bit 0 = 1). This MSR is generally
configured by the BIOS using WRMSR.
• Execute VMXON with the physical address of the VMXON region as the operand.
Check successful execution of VMXON by checking if RFLAGS.CF = 0.
Upon successful execution of the steps above, the processor is in VMX root operation.
A VMM executing in VMX root operation and CPL = 0 leaves VMX operation by
executing VMXOFF and verifies successful execution by checking if RFLAGS.CF = 0
and RFLAGS.ZF = 0.
If an SMM monitor has been configured to service SMIs while in VMX operation (see
Section 25.15), the SMM monitor needs to be torn down before the executive
monitor can leave VMX operation (see Section 25.15.7). VMXOFF fails for the execu-
tive monitor (a VMM that entered VMX operation by way of issuing VMXON) if SMM
monitor is configured.
26.5.1 Algorithms for Determining VMX Capabilities
As noted earlier, a VMM should determine the VMX capabilities supported by the
processor by reading the VMX capability MSRs. The architecture for these MSRs is
detailed in Appendix G.
As noted in Chapter 20, “Virtual-Machine Control Structures”, certain VMX controls
are reserved and must be set to a specific value (0 or 1) determined by the processor.
The specific value to which a reserved control must be set is its default setting.
Most controls have a default setting of 0; Appendix G.2 identifies those controls that
have a default setting of 1. The term default1 describes the class of controls whose
default setting is 1. The are controls in this class from the pin-based VM-execution
controls, the primary processor-based VM-execution controls, the VM-exit controls,
and the VM-entry controls. There are no secondary processor-based VM-execution
controls in the default1 class.
Future processors may define new functionality for one or more reserved controls.
Such processors would allow each newly defined control to be set either to 0 or to 1.
Software that does not desire a control’s new functionality should set the control to
its default setting.
The capability MSRs IA32_VMX_PINBASED_CTLS, IA32_VMX_PROCBASED_CTLS,
IA32_VMX_EXIT_CTLS, and IA32_VMX_ENTRY_CTLS report, respectively, on the
allowed settings of most of the pin-based VM-execution controls, the primary
processor-based VM-execution controls, the VM-exit controls, and the VM-entry
controls. However, they will always report that any control in the default1 class must
be 1. If a logical processor allows any control in the default1 class to be 0, it indicates
this fact by returning 1 for the value of bit 55 of the IA32_VMX_BASIC MSR. If this bit