Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

26-10 Vol. 3
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
upon subsequent VM exits from the guest. Host-state fields include control
registers (CR0, CR3 and CR4), selector fields for the segment registers (CS, SS,
DS, ES, FS, GS and TR), and base-address fields (for FS, GS, TR, GDTR and IDTR;
RSP, RIP and the MSRs that control fast system calls).
Chapter 22 describes the host-state consistency checking done by the processor
for VM entries. The VMM is required to set up host-state that comply with these
consistency checks. For example, VMX requires the host-area to have a task
register (TR) selector with TI and RPL fields set to 0 and pointing to a valid TSS.
• Use VMWRITEs to set up the various VM-exit control fields, VM-entry control
fields, and VM-execution control fields in the VMCS. Care should be taken to
make sure the settings of individual fields match the allowed 0 and 1 settings for
the respective controls as reported by the VMX capability MSRs (see Appendix G).
Any settings inconsistent with the settings reported by the capability MSRs will
cause VM entries to fail.
• Use VMWRITE to initialize various guest-state area fields in the working VMCS.
This sets up the context and entry-point for guest execution upon VM entry.
Chapter 22 describes the guest-state loading and checking done by the processor
for VM entries to protected and virtual-8086 guest execution.
• The VMM is required to set up guest-state that complies with these consistency
checks:
— If the VMM design requires the initial VM launch to cause guest software
(typically the guest virtual BIOS) execution from the guest’s reset vector, it
may need to initialize the guest execution state to reflect the state of a
physical processor at power-on reset (described in Chapter 8, Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A).
— The VMM may need to initialize additional guest execution state that is not
captured in the VMCS guest-state area by loading them directly on the
respective processor registers. Examples include general purpose registers,
the CR2 control register, debug registers, floating point registers and so forth.
VMM may support lazy loading of FPU, MMX, SSE, and SSE2 states with
CR0.TS = 1 (described in Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3A).
• Execute VMLAUNCH to launch the guest VM. If VMLAUNCH fails due to any
consistency checks before guest-state loading, RFLAGS.CF or RFLAGS.ZF will be
set and the VM-instruction error field (see Section 20.9.5) will contain the error-
code. If guest-state consistency checks fail upon guest-state loading, the
processor loads state from the host-state area as if a VM exit had occurred (see
Section 26.6).
VMLAUNCH updates the controlling-VMCS pointer with the working-VMCS pointer
and saves the old value of controlling-VMCS as the parent pointer. In addition, the
launch state of the guest VMCS is changed to “launched” from “clear”. Any
programmed exit conditions will cause the guest to VM exit to the VMM. The VMM
should execute VMRESUME instruction for subsequent VM entries to guests in a
“launched” state.