Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 26-19
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
these fields write 64-bits. When outside of 64-bit mode, reads of these fields return
the low 32-bits and writes to these fields write the low 32-bits and zero the upper
32-bits. Should a non-IA-32e mode host require access to the upper 32-bits of these
fields, a separate VMCS encoding is used when issuing VMREAD/VMWRITE instruc-
tions.
The VMCS control field “MSR bitmap address” (which contains the physical address of
a region of memory which specifies which MSR accesses should generate VM-exits) is
an example of this type of field. Specifying encoding 00002004H to VMREAD returns
the lower 32-bits to non-IA-32e mode hosts and returns 64-bits to 64-bit hosts. The
separate encoding 00002005H returns only the upper 32-bits.
26.9.3 IA-32e Mode Hosts
An IA-32e mode host is required to support 64-bit guest environments. Because acti-
vating IA-32e mode currently requires that paging be disabled temporarily and VMX
entry requires paging to be enabled, IA-32e mode must be enabled before entering
VMX operation. For this reason, it is not possible to toggle in and out of IA-32e mode
in a VMM.
Section 26.5 describes the steps required to launch a VMM. An IA-32e mode host is
also required to set the “host address-space size” VMCS VM-exit control to 1. The
value of this control is then loaded in the IA32_EFER.LME/LMA and CS.L bits on each
VM exit. This establishes a 64-bit host environment as execution transfers to the
VMM entry point. At a minimum, the entry point is required to be in a 64-bit code
segment. Subsequently, the VMM can, if it chooses, switch to 32-bit compatibility
mode on a code-segment basis (see Section 26.9.1). Note, however, that VMX
instructions other than VMCALL are not supported in compatibility mode; they
generate an invalid opcode exception if used.
The following VMCS controls determine the value of IA32_EFER when a VM exit
occurs: the “host address-space size” control (described above), the “load
IA32_EFER” VM-exit control, the “VM-exit MSR-load count,” and the “VM-exit MSR-
load address” (see Section 23.3).
If the “load IA32_EFER” VM-exit control is 1, the value of the LME and LMA bits in the
IA32_EFER field in the host-state area must be the value of the “host address-space
size” VM-exit control.
The loading of IA32_EFER.LME/LMA and CS.L bits established by the “host address-
space size” control precede any loading of the IA32_EFER MSR due from the VM-exit
MSR-load area. If IA32_EFER is specified in the VM-exit MSR-load area, the value of
the LME bit in the load image of IA32_EFER should match the setting of the “host
address-space size” control. Otherwise the attempt to modify the LME bit (while
paging is enabled) will lead to a VMX-abort. However, IA32_EFER.LMA is always set
by the processor to equal IA32_EFER.LME & CR0.PG; the value specified for LMA in
the load image of the IA32_EFER MSR is ignored. For these and performance
reasons, VMM writers may choose to not use the VM-exit/entry MSR-load/save areas
for IA32_EFER.