Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 26-21
VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS
A VMM should save/restore the extended (full 64-bit) contents of the guest general-
purpose registers, the new general-purpose registers (R8-R15) and the SIMD regis-
ters introduced in 64-bit mode should it need to modify these upon VM exit.
26.9.5 32-Bit Guests
To launch or resume a 32-bit guest, VMM writers can follow the steps outlined in
Section 26.6, making sure that the “IA-32e-mode guest” VM-entry control bit is set
to 0. Then the “IA-32e-mode guest” control bit is copied into the guest
IA32_EFER.LME bit, establishing IA32_EFER.LMA as 0.
26.10 HANDLING MODEL SPECIFIC REGISTERS
Model specific registers (MSR) provide a wide range of functionality. They affect
processor features, control the programming interfaces, or are used in conjunction
with specific instructions. As part of processor virtualization, a VMM may wish to
protect some or all MSR resources from direct guest access.
VMX operation provides the following features to virtualize processor MSRs.
26.10.1 Using VM-Execution Controls
Processor-based VM-execution controls provide two levels of support for handling
guest access to processor MSRs using RDMSR and WRMSR:
• MSR bitmaps: In VMX implementations that support a 1-setting (see Appendix
G) of the user-MSR-bitmaps execution control bit, MSR bitmaps can be used to
provide flexibility in managing guest MSR accesses. The MSR-bitmap-address in
the guest VMCS can be programmed by VMM to point to a bitmap region which
specifies VM-exit behavior when reading and writing individual MSRs.
MSR bitmaps form a 4-KByte region in physical memory and are required to be
aligned to a 4-KByte boundary. The first 1-KByte region manages read control of
MSRs in the range 00000000H-00001FFFH; the second 1-KByte region covers
read control of MSR addresses in the range C0000000H-C0001FFFH. The bitmaps
for write control of these MSRs are located in the 2-KByte region immediately
following the read control bitmaps. While the MSR bitmap address is part of
VMCS, the MSR bitmaps themselves are not. This implies MSR bitmaps are not
accessible through VMREAD and VMWRITE instructions but rather by using
ordinary memory writes. Also, they are not specially cached by the processor and
may be placed in normal cache-coherent memory by the VMM.
When MSR bitmap addresses are properly programmed and the use-MSR-bitmap
control (see Section 20.6.2) is set, the processor consults the associated bit in
the appropriate bitmap on guest MSR accesses to the corresponding MSR and
causes a VM exit if the bit in the bitmap is set. Otherwise, the access is permitted