Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

27-10 Vol. 3
VIRTUALIZATION OF SYSTEM RESOURCES
8. Consult the active PTE, which can be located using the next 10 bits of the faulting
address (bits 21–12) and the physical page-table base address in the active PDE.
The active PTE is the source of the fault if it is marked not-present or if its R/W bit
and U/S bits are inconsistent with the attempted guest access (the guest
privilege level and the value of CR0:WP should also be taken into account).
9. If the active PTE is not the source of the fault, then the fault has resulted from an
inconsistency between the active page-table hierarchy and the processor’s TLB.
Since the transition to the VMM caused an address-space change and flushed the
processor’s TLB, the VMM simply re-executes the faulting instruction.
The remaining steps assume that the active PTE is the source of the fault.
10. Consult the corresponding guest PTE using the same 10 bits from the faulting
address and the physical address that correspond to the guest page-table base
address in the guest PDE. If the guest PTE would cause a page fault (it is marked
not-present), the raise a page fault to the guest operating system.
The following steps assume that the guest PTE would not have caused a page
fault.
11. If the guest PTE contains, as page base address, a physical address that is not
valid for the virtual machine being supported; then raise a machine check (or
some other abort) to the guest operating system.
The following steps assume that the address in the guest PTE is valid for the
virtual machine.
12. If the active PTE is marked not-present, then set the active PTE to correspond to
guest PTE:
a. Set the page base address in the active PTE to be the physical address that
corresponds to the guest page base address in the guest PTE.
b. Set the P, U/S, and PS bits in the active PTE to be identical to those in the
guest PTE.
c. Set the PWT, PCD, and G bits according to the policy of the VMM.
d. Set A = 1 in the guest PTE.
e. If D = 1 in the guest PTE, then set the R/W bit in the active PTE as in the
guest PTE.
f. If D = 0 in the guest PTE and the attempted access is a write, then set R/W in
the active PTE as in the guest PTE and set D = 1 in the guest PTE.
g. If D = 0 in the guest PTE and the attempted access is not a write, then set
R/W = 0 in the active PTE.
h. After modifying the active PTE, re-execute the faulting instruction.
The remaining steps assume that the active PTE is already marked present.
13. If the attempted access is a write, D = 0 (not dirty) in the guest PTE and the
active PTE has caused a fault solely because it has R/W = 0 (read-only); then set