Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 27-11
VIRTUALIZATION OF SYSTEM RESOURCES
R/W in the active PTE as in the guest PTE, set D = 1 in the guest PTE and re-
execute the faulting instruction.
14. If none of the above cases apply, then raise a page fault of the guest operating
system.
27.3.5.3 Response to Uses of INVLPG
Operating-systems can use INVLPG to flush entries from the TLB. This instruction
takes a linear address as an operand and software expects any cached translations
for the address to be flushed. VMM should set the processor-based VMCS execution
control invplg-exiting = 1, such that any attempts by a privileged guest to execute
INVLPG will trap to the VMM (attempts to execute INVLPG by unprivileged guest are
managed by the exception bitmap control in the VMCS). The VMM can then modify
the active page-table hierarchy to emulate the desired effect of the INVLPG.
The following steps are performed. Note that these steps are performed only if the
guest invocation of INVLPG would not fault and only if the guest software is running
at privilege level 0:
1. Locate the relevant active PDE using the upper 10 bits of the operand address
and the current value of CR3. If the PDE refers to a 4-MByte page (PS = 1), then
set P = 0 in the PDE.
2. If the PDE is marked present and refers to a page table (PS = 0), locate the
relevant active PTE using the next 10 bits of the operand address (bits 21–12)
and the page-table base address in the PDE. Set P = 0 in the PTE. Examine all
PTEs in the page table; if they are now all marked not-present, de-allocate the
page table and set P = 0 in the PDE (this step may be optional).
27.3.5.4 Response to CR3 Writes
A guest operating system may attempt to write to CR3. Any write to CR3 implies a
TLB flush and a possible page table change. The following steps are performed:
1. The VMM notes the new CR3 value (used later to walk guest page tables) and
emulates the write.
2. The VMM allocates a new PD page, with all invalid entries.
3. The VMM sets actual processor CR3 register to point to the new PD page.
The VMM may, at this point, speculatively fill in VTLB mappings for performance
reasons.
27.4 MICROCODE UPDATE FACILITY
The microcode code update facility may be invoked at various points during the oper-
ation of a platform. Typically, the BIOS invokes the facility on all processors during