Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-15
PERFORMANCE-MONITORING EVENTS
42H 02H L1D_CACHE_LOCK.S_
STATE
Counts L1 data cache retired load
locks that hit the target cache line
in the shared state.
Counter 0, 1 only
42H 04H L1D_CACHE_LOCK.E_
STATE
Counts L1 data cache retired load
locks that hit the target cache line
in the exclusive state.
Counter 0, 1 only
42H 08H L1D_CACHE_LOCK.M
_STATE
Counts L1 data cache retired load
locks that hit the target cache line
in the modified state.
Counter 0, 1 only
43H 01H L1D_ALL_REF.ANY Counts all references (uncached,
speculated and retired) to the L1
data cache, including all loads and
stores with any memory types. The
event counts memory accesses
only when they are actually
performed. For example, a load
blocked by unknown store address
and later performed is only counted
once.
The event does
not include non-
memory
accesses, such as
I/O accesses.
Counter 0, 1 only
43H 02H L1D_ALL_REF.CACHE
ABLE
Counts all data reads and writes
(speculated and retired) from
cacheable memory, including locked
operations.
Counter 0, 1 only
48H 02H L1D_PEND_MISS.LOA
D_BUFFERS_FULL
Counts cycles of L1 data cache load
fill buffers full.
Counter 0, 1 only
49H 01H DTLB_MISSES.ANY Counts the number of misses in the
STLB which causes a page walk.
49H 02H DTLB_MISSES.WALK_
COMPLETED
Counts number of misses in the
STLB which resulted in a completed
page walk.
49H 10H DTLB_MISSES.STLB_
HIT
Counts the number of DTLB first
level misses that hit in the second
level TLB. This event is only
relevant if the core contains
multiple DTLB levels.
49H 20H DTLB_MISSES.PDE_M
ISS
Number of DTLB cache misses
where the low part of the linear to
physical address translation was
missed.
Table A-2. Non-Architectural Performance Events In the Processor Core for Intel Core
i7 Processors
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment