Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-22 Vol. 3
PERFORMANCE-MONITORING EVENTS
89H 7FH BR_MISP_EXEC.ANY Counts the number of mispredicted
near branch instructions that were
executed, but not necessarily
retired.
A2H 01H RESOURCE_STALLS.
ANY
Counts the number of Allocator
resource related stalls. Includes
register renaming buffer entries,
memory buffer entries. In addition
to resource related stalls, this event
counts some other events. Includes
stalls arising during branch
misprediction recovery, such as if
retirement of the mispredicted
branch is delayed and stalls arising
while store buffer is draining from
synchronizing operations.
Does not include
stalls due to
SuperQ (off core)
queue full, too
many cache
misses, etc.
A2H 02H RESOURCE_STALLS.L
OAD
Counts the cycles of stall due to
lack of load buffer for load
operation.
A2H 04H RESOURCE_STALLS.R
S_FULL
This event counts the number of
cycles when the number of
instructions in the pipeline waiting
for execution reaches the limit the
processor can handle. A high count
of this event indicates that there
are long latency operations in the
pipe (possibly load and store
operations that miss the L2 cache,
or instructions dependent upon
instructions further down the
pipeline that have yet to retire.
When RS is full,
new instructions
can not enter the
reservation
station and start
execution.
A2H 08H RESOURCE_STALLS.S
TORE
This event counts the number of
cycles that a resource related stall
will occur due to the number of
store instructions reaching the limit
of the pipeline, (i.e. all store buffers
are used). The stall ends when a
store instruction commits its data
to the cache or memory.
A2H 10H RESOURCE_STALLS.R
OB_FULL
Counts the cycles of stall due to re-
order buffer full.
Table A-2. Non-Architectural Performance Events In the Processor Core for Intel Core
i7 Processors
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment