Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-43
DEBUGGING AND PERFORMANCE MONITORING
NOTE
To determine average processor clock frequency, Intel recommends
the use of EMON logic to count processor core clocks over the period
of time for which the average is required. See Section 18.20,
“Counting Clocks,” and Appendix A, “Performance-
Monitoring Events,” for more information.
The RDTSC instruction reads the time-stamp counter and is guaranteed to return a
monotonically increasing unique value whenever executed, except for a 64-bit
counter wraparound. Intel guarantees that the time-stamp counter will not wrap-
around within 10 years after being reset. The period for counter wrap is longer for
Pentium 4, Intel Xeon, P6 family, and Pentium processors.
Normally, the RDTSC instruction can be executed by programs and procedures
running at any privilege level and in virtual-8086 mode. The TSD flag allows use of
this instruction to be restricted to programs and procedures running at privilege level
0. A secure operating system would set the TSD flag during system initialization to
disable user access to the time-stamp counter. An operating system that disables
user access to the time-stamp counter should emulate the instruction through a
user-accessible programming interface.
The RDTSC instruction is not serializing or ordered with other instructions. It does not
necessarily wait until all previous instructions have been executed before reading the
counter. Similarly, subsequent instructions may begin execution before the RDTSC
instruction operation is performed.
The RDMSR and WRMSR instructions read and write the time-stamp counter, treating
the time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel
Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using
RDMSR (just as with RDTSC). When WRMSR is used to write the time-stamp counter
on processors before family [0FH], models [03H, 04H]: only the low-order 32-bits of
the time-stamp counter can be written (the high-order 32 bits are cleared to 0). For
family [0FH], models [03H, 04H, 06H]; for family [06H]], model [0EH, 0FH]; for
family [06H]], display_model [17H, 1AH, 1CH, 1DH]: all 64 bits are writable.
18.11.1 Invariant TSC
The time stamp counter in newer processors may support an enhancement, referred
to as invariant TSC. Processor’s support for invariant TSC is indicated by
CPUID.0x80000007.EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-. and T-states. This is
the architectural behavior moving forward. On processors with invariant TSC
support, the OS may use the TSC for wall clock timer services (instead of ACPI or
HPET timers). TSC reads are much more efficient and do not incur the overhead
associated with a ring transition or access to a platform resource.