Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-44 Vol. 3
PERFORMANCE-MONITORING EVENTS
27H 10H UNC_QMC_NORMAL_
FULL.WRITE.CH1
Counts cycles all the entries in the
DRAM channel 1 medium or low
priority queue are occupied with
write requests.
27H 20H UNC_QMC_NORMAL_
FULL.WRITE.CH2
Uncore cycles all the entries in the
DRAM channel 2 medium or low
priority queue are occupied with
write requests.
28H 01H UNC_QMC_ISOC_FUL
L.READ.CH0
Counts cycles all the entries in the
DRAM channel 0 high priority queue
are occupied with isochronous read
requests.
28H 02H UNC_QMC_ISOC_FUL
L.READ.CH1
Counts cycles all the entries in the
DRAM channel 1high priority queue
are occupied with isochronous read
requests.
28H 04H UNC_QMC_ISOC_FUL
L.READ.CH2
Counts cycles all the entries in the
DRAM channel 2 high priority queue
are occupied with isochronous read
requests.
28H 08H UNC_QMC_ISOC_FUL
L.WRITE.CH0
Counts cycles all the entries in the
DRAM channel 0 high priority queue
are occupied with isochronous
write requests.
28H 10H UNC_QMC_ISOC_FUL
L.WRITE.CH1
Counts cycles all the entries in the
DRAM channel 1 high priority queue
are occupied with isochronous
write requests.
28H 20H UNC_QMC_ISOC_FUL
L.WRITE.CH2
Counts cycles all the entries in the
DRAM channel 2 high priority queue
are occupied with isochronous
write requests.
29H 01H UNC_QMC_BUSY.REA
D.CH0
Counts cycles where Quickpath
Memory Controller has at least 1
outstanding read request to DRAM
channel 0.
Table A-3. Non-Architectural Performance Events In the Processor Uncore for Intel
Core i7 Processors
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment