Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-45
PERFORMANCE-MONITORING EVENTS
29H 02H UNC_QMC_BUSY.REA
D.CH1
Counts cycles where Quickpath
Memory Controller has at least 1
outstanding read request to DRAM
channel 1.
29H 04H UNC_QMC_BUSY.REA
D.CH2
Counts cycles where Quickpath
Memory Controller has at least 1
outstanding read request to DRAM
channel 2.
29H 08H UNC_QMC_BUSY.WRI
TE.CH0
Counts cycles where Quickpath
Memory Controller has at least 1
outstanding write request to
DRAM channel 0.
29H 10H UNC_QMC_BUSY.WRI
TE.CH1
Counts cycles where Quickpath
Memory Controller has at least 1
outstanding write request to
DRAM channel 1.
29H 20H UNC_QMC_BUSY.WRI
TE.CH2
Counts cycles where Quickpath
Memory Controller has at least 1
outstanding write request to
DRAM channel 2.
2CH 01H UNC_QMC_NORMAL_
READS.CH0
Counts the number of Quickpath
Memory Controller channel 0
medium and low priority read
requests. The QMC channel 0
normal read occupancy divided by
this count provides the average
QMC channel 0 read latency.
2CH 02H UNC_QMC_NORMAL_
READS.CH1
Counts the number of Quickpath
Memory Controller channel 1
medium and low priority read
requests. The QMC channel 1
normal read occupancy divided by
this count provides the average
QMC channel 1 read latency.
Table A-3. Non-Architectural Performance Events In the Processor Uncore for Intel
Core i7 Processors
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment