Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-53
PERFORMANCE-MONITORING EVENTS
60H 02H UNC_DRAM_OPEN.C
H1
Counts number of DRAM Channel 1
open commands issued either for
read or write. To read or write data,
the referenced DRAM page must
first be opened.
60H 04H UNC_DRAM_OPEN.C
H2
Counts number of DRAM Channel 2
open commands issued either for
read or write. To read or write data,
the referenced DRAM page must
first be opened.
61H 01H UNC_DRAM_PAGE_C
LOSE.CH0
DRAM channel 0 command issued
to CLOSE a page due to page idle
timer expiration. Closing a page is
done by issuing a precharge.
61H 02H UNC_DRAM_PAGE_C
LOSE.CH1
DRAM channel 1 command issued
to CLOSE a page due to page idle
timer expiration. Closing a page is
done by issuing a precharge.
61H 04H UNC_DRAM_PAGE_C
LOSE.CH2
DRAM channel 2 command issued
to CLOSE a page due to page idle
timer expiration. Closing a page is
done by issuing a precharge.
62H 01H UNC_DRAM_PAGE_M
ISS.CH0
Counts the number of precharges
(PRE) that were issued to DRAM
channel 0 because there was a
page miss. A page miss refers to a
situation in which a page is
currently open and another page
from the same bank needs to be
opened. The new page experiences
a page miss. Closing of the old page
is done by issuing a precharge.
Table A-3. Non-Architectural Performance Events In the Processor Uncore for Intel
Core i7 Processors
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment