Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-56 Vol. 3
PERFORMANCE-MONITORING EVENTS
A.3 PERFORMANCE MONITORING EVENTS FOR
INTEL
®
XEON
®
PROCESSOR 5200, 5400 SERIES
65H 02H UNC_DRAM_REFRES
H.CH1
Counts number of DRAM channel 1
refresh commands. DRAM loses
data content over time. In order to
keep correct data content, the data
values have to be refreshed
periodically.
65H 04H UNC_DRAM_REFRES
H.CH2
Counts number of DRAM channel 2
refresh commands. DRAM loses
data content over time. In order to
keep correct data content, the data
values have to be refreshed
periodically.
66H 01H UNC_DRAM_PRE_AL
L.CH0
Counts number of DRAM Channel 0
precharge-all (PREALL) commands
that close all open pages in a rank.
PREALL is issued when the DRAM
needs to be refreshed or needs to
go into a power down mode.
66H 02H UNC_DRAM_PRE_AL
L.CH1
Counts number of DRAM Channel 1
precharge-all (PREALL) commands
that close all open pages in a rank.
PREALL is issued when the DRAM
needs to be refreshed or needs to
go into a power down mode.
66H 04H UNC_DRAM_PRE_AL
L.CH2
Counts number of DRAM Channel 2
precharge-all (PREALL) commands
that close all open pages in a rank.
PREALL is issued when the DRAM
needs to be refreshed or needs to
go into a power down mode.
Table A-3. Non-Architectural Performance Events In the Processor Uncore for Intel
Core i7 Processors
Event
Num.
Umask
Value
Event Mask
Mnemonic Description Comment