Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-58 Vol. 3
PERFORMANCE-MONITORING EVENTS
Table A-6 lists general-purpose non-architectural performance-monitoring events
supported in processors based on Intel Core microarchitecture. For convenience,
Table A-6 also includes architectural events and describes minor model-specific
Table A-5. Fixed-Function Performance Counter
and Pre-defined Performance Events
Fixed-Function
Performance
Counter Address
Event Mask
Mnemonic Description
MSR_PERF_FIXED_
CTR0
309H Instr_Retired.Any This event counts the number of
instructions that retire execution. For
instructions that consist of multiple micro-
ops, this event counts the retirement of
the last micro-op of the instruction. The
counter continue counting during
hardware interrupts, traps, and inside
interrupt handlers
MSR_PERF_FIXED_
CTR1
30AH CPU_CLK_UNHALT
ED.CORE
This event counts the number of core
cycles while the core is not in a halt state.
The core enters the halt state when it is
running the HLT instruction. This event is a
component in many key event ratios.
The core frequency may change from time
to time due to transitions associated with
Enhanced Intel SpeedStep Technology or
TM2. For this reason this event may have
a changing ratio with regards to time.
When the core frequency is constant, this
event can approximate elapsed time while
the core was not in halt state.
MSR_PERF_FIXED_
CTR2
30BH CPU_CLK_UNHALT
ED.REF
This event counts the number of
reference cycles when the core is not in a
halt state. The core enters the halt state
when it is running the HLT instruction or
the MWAIT instruction.
This event is not affected by core
frequency changes (e.g., P states, TM2
transitions) but counts at the same
frequency as the time stamp counter. This
event can approximate elapsed time while
the core was not in halt state.
This event has a constant ratio with the
CPU_CLK_UNHALTED.BUS event.