Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-68 Vol. 3
PERFORMANCE-MONITORING EVENTS
26HSee
Table
18-11
and
Table
18-13
L2_LINES_OUT.
(Core, Prefetch)
L2 cache lines
evicted
This event counts the number of L2 cache
lines evicted.
This event can count occurrences for this
core or both cores. It can also count
evictions due to demand requests and L2
hardware prefetch requests together or
separately.
27HSee
Table
18-11
and
Table
18-13
L2_M_LINES_OUT.(
Core, Prefetch)
Modified lines
evicted from
the L2 cache
This event counts the number of L2
modified cache lines evicted. These lines
are written back to memory unless they
also exist in a modified-state in one of the
L1 data caches.
This event can count occurrences for this
core or both cores. It can also count
evictions due to demand requests and L2
hardware prefetch requests together or
separately.
28H Com-
bined
mask
from
Table
18-11
and
Table
18-14
L2_IFETCH.(Core,
Cache Line State)
L2 cacheable
instruction
fetch requests
This event counts the number of
instruction cache line requests from the
IFU. It does not include fetch requests
from uncacheable memory. It does not
include ITLB miss accesses.
This event can count occurrences for this
core or both cores. It can also count
accesses to cache lines at different MESI
states.
29H Combin
ed mask
from
Table
18-11,
Table
18-13,
and
Table
18-14
L2_LD.(Core,
Prefetch, Cache
Line State)
L2 cache reads This event counts L2 cache read requests
coming from the L1 data cache and L2
prefetchers.
The event can count occurrences:
• for this core or both cores
• due to demand requests and L2
hardware prefetch requests together or
separately
• of accesses to cache lines at different
MESI states
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment