Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-70 Vol. 3
PERFORMANCE-MONITORING EVENTS
30HSee
Table
18-11,
Table
18-13,
and
Table
18-14
L2_REJECT_BUSQ.(
Core, Prefetch,
Cache Line State)
Rejected L2
cache requests
This event indicates that a pending L2
cache request that requires a bus
transaction is delayed from moving to the
bus queue. Some of the reasons for this
event are:
• The bus queue is full.
• The bus queue already holds an entry
for a cache line in the same set.
The number of events is greater or equal
to the number of requests that were
rejected.
• for this core or both cores.
• due to demand requests and L2
hardware prefetch requests together,
or separately.
• of accesses to cache lines at different
MESI states.
32HSee
Table
18-11
L2_NO_REQ.(Core) Cycles no L2
cache requests
are pending
This event counts the number of cycles
that no L2 cache requests were pending
from a core. When using the BOTH_CORE
modifier, the event counts only if none of
the cores have a pending request. The
event counts also when one core is halted
and the other is not halted.
The event can count occurrences for this
core or both cores.
3AH 00H EIST_TRANS Number of
Enhanced Intel
SpeedStep
Technology
(EIST)
transitions
This event counts the number of
transitions that include a frequency
change, either with or without voltage
change. This includes Enhanced Intel
SpeedStep Technology (EIST) and TM2
transitions.
The event is incremented only while the
counting core is in C0 state. Since
transitions to higher-numbered CxE states
and TM2 transitions include a frequency
change or voltage transition, the event is
incremented accordingly.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment