Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

A-72 Vol. 3
PERFORMANCE-MONITORING EVENTS
3CH 02HCPU_CLK_
UNHALTED.NO
_OTHER
Bus cycles
when core is
active and the
other is halted
This event counts the number of bus
cycles during which the core remains non-
halted and the other core on the processor
is halted.
This event can be used to determine the
amount of parallelism exploited by an
application or a system. Divide this event
count by the bus frequency to determine
the amount of time that only one core was
in use.
40HSee
Table
18-14
L1D_CACHE_LD.
(Cache Line State)
L1 cacheable
data reads
This event counts the number of data
reads from cacheable memory. Locked
reads are not counted.
41HSee
Table
18-14
L1D_CACHE_ST.
(Cache Line State)
L1 cacheable
data writes
This event counts the number of data
writes to cacheable memory. Locked
writes are not counted.
42HSee
Table
18-14
L1D_CACHE_
LOCK.(Cache Line
State)
L1 data
cacheable
locked reads
This event counts the number of locked
data reads from cacheable memory.
42H 10HL1D_CACHE_
LOCK_DURATION
Duration of L1
data cacheable
locked
operation
This event counts the number of cycles
during which any cache line is locked by
any locking instruction.
Locking happens at retirement and
therefore the event does not occur for
instructions that are speculatively
executed. Locking duration is shorter than
locked instruction execution duration.
43H 01H L1D_ALL_REF All references
to the L1 data
cache
This event counts all references to the L1
data cache, including all loads and stores
with any memory types.
The event counts memory accesses only
when they are actually performed. For
example, a load blocked by unknown store
address and later performed is only
counted once.
The event includes non-cacheable
accesses, such as I/O accesses.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment