Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 A-73
PERFORMANCE-MONITORING EVENTS
43H 02HL1D_ALL_
CACHE_REF
L1 Data
cacheable
reads and
writes
This event counts the number of data
reads and writes from cacheable memory,
including locked operations.
This event is a sum of:
•L1D_CACHE_LD.MESI
•L1D_CACHE_ST.MESI
•L1D_CACHE_LOCK.MESI
45H 0FHL1D_REPL Cache lines
allocated in the
L1 data cache
This event counts the number of lines
brought into the L1 data cache.
46H 00H L1D_M_REPL Modified cache
lines allocated
in the L1 data
cache
This event counts the number of modified
lines brought into the L1 data cache.
47H 00H L1D_M_EVICT Modified cache
lines evicted
from the L1
data cache
This event counts the number of modified
lines evicted from the L1 data cache,
whether due to replacement or by snoop
HITM intervention.
48H 00HL1D_PEND_
MISS
Total number of
outstanding L1
data cache
misses at any
cycle
This event counts the number of
outstanding L1 data cache misses at any
cycle. An L1 data cache miss is
outstanding from the cycle on which the
miss is determined until the first chunk of
data is available. This event counts:
• all cacheable demand requests
• L1 data cache hardware prefetch
requests
• requests to write through memory
• requests to write combine memory
Uncacheable requests are not counted.
The count of this event divided by the
number of L1 data cache misses,
L1D_REPL, is the average duration in core
cycles of an L1 data cache miss.
49H 01H L1D_SPLIT.LOADS Cache line split
loads from the
L1 data cache
This event counts the number of load
operations that span two cache lines. Such
load operations are also called split loads.
Split load operations are executed at
retirement.
Table A-6. Non-Architectural Performance Events
in Processors Based on Intel Core Microarchitecture (Contd.)
Event
Num
Umask
Value Event Name Definition
Description and
Comment